forked from github/verilator
9 lines
215 B
Systemverilog
9 lines
215 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (portwithoin);
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input portwithin;
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endmodule
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