forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 |
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| .. | ||
| figures | ||
| changes.rst | ||
| conf.py | ||
| connecting.rst | ||
| contributing.rst | ||
| contributors.rst | ||
| copyright.rst | ||
| deprecations.rst | ||
| environment.rst | ||
| example_cc.rst | ||
| example_common_install.rst | ||
| example_dist.rst | ||
| example_sc.rst | ||
| examples.rst | ||
| exe_sim.rst | ||
| exe_verilator_coverage.rst | ||
| exe_verilator_gantt.rst | ||
| exe_verilator_profcfunc.rst | ||
| exe_verilator.rst | ||
| executables.rst | ||
| extensions.rst | ||
| faq.rst | ||
| files.rst | ||
| index.rst | ||
| install.rst | ||
| languages.rst | ||
| overview.rst | ||
| simulating.rst | ||
| verilating.rst | ||
| warnings.rst | ||