Wilson Snyder
|
4e522ab7f5
|
Fix define formal arguments that contain newlines, bug84.
|
2009-05-11 11:57:43 -04:00 |
|
Wilson Snyder
|
96d150e92d
|
Verilator_includer is no longer installed twice, bug48.
|
2009-05-08 15:05:12 -04:00 |
|
Wilson Snyder
|
592b2e76a8
|
Prepatory code for tracing escaped dots
|
2009-05-08 14:48:33 -04:00 |
|
Wilson Snyder
|
a3e463030d
|
Fix escaped identifiers with '.' causing conflicts, bug83.
|
2009-05-08 13:16:19 -04:00 |
|
Wilson Snyder
|
4569278c53
|
Reconsile parser with Verilog-Perl version, to enable more SV features
|
2009-05-07 18:28:05 -04:00 |
|
Wilson Snyder
|
851b022c7a
|
Change lexer to more closely match Verilog-Perl. Should be no functional change
|
2009-05-05 13:39:25 -04:00 |
|
Wilson Snyder
|
0985f675e3
|
Update bisonpre to match Verilog-Perl version
|
2009-05-04 21:54:44 -04:00 |
|
Wilson Snyder
|
7df730cedd
|
Verilator is now licensed under LGPL v3 and/or Artistic v2.0.
|
2009-05-04 17:07:57 -04:00 |
|
Wilson Snyder
|
314ffd9353
|
Version bump
|
2009-05-02 07:38:24 -04:00 |
|
Wilson Snyder
|
2c953dc37f
|
Fix $clog2 calculation error with powers-of-2, bug81.
|
2009-05-01 22:18:32 -04:00 |
|
Wilson Snyder
|
9b9e4e5a3f
|
Fix "redefining I" error with complex includes.
|
2009-04-28 07:19:50 -04:00 |
|
Wilson Snyder
|
50f835c701
|
Fix segfault with error on bad --top-module, bug79.
|
2009-04-24 10:32:11 -04:00 |
|
Wilson Snyder
|
cbb3351d97
|
Fix GCC 4.3.2 compile warnings.
|
2009-04-23 09:16:25 -04:00 |
|
Wilson Snyder
|
fb81721e7e
|
Add missing files from last bug
|
2009-04-23 09:13:55 -04:00 |
|
Wilson Snyder
|
2cedef1333
|
Avoid config_rev making empty file on errors
|
2009-04-23 09:11:40 -04:00 |
|
Wilson Snyder
|
4a1697a1b5
|
Fix GCC format warning
|
2009-04-08 21:47:48 -04:00 |
|
Wilson Snyder
|
86f08a341c
|
Fix error with tasks that have output first, bug78.
|
2009-04-08 14:33:12 -04:00 |
|
Wilson Snyder
|
3d85cbe6b5
|
Fix "cloning" error with -y/--top-module, bug76.
|
2009-04-07 13:23:25 -04:00 |
|
Wilson Snyder
|
6d3dd98e77
|
Fix "cloning" error with -y/--top-module, bug76.
Caused by missorting top-module cells; so move code from V3LinkLevel into
V3LinkCells.
|
2009-04-06 22:26:38 -04:00 |
|
Wilson Snyder
|
9b2004d6b7
|
Commentary
|
2009-04-03 17:26:34 -04:00 |
|
Wilson Snyder
|
eb072da81c
|
Version bump
|
2009-03-28 10:30:35 -04:00 |
|
Wilson Snyder
|
38669d0a10
|
Add SYSTEMPERL_INCLUDE envvar to assist RPM builds.
|
2009-03-28 10:18:53 -04:00 |
|
Wilson Snyder
|
202a8bc3bb
|
Internals: Use common wrapper for setenv
|
2009-03-28 09:15:13 -04:00 |
|
Wilson Snyder
|
45e8ed6b49
|
Internals: Cleanup what symbol lookups need to recurse up vs not.
|
2009-03-24 09:22:58 -04:00 |
|
Wilson Snyder
|
96692e8a5b
|
Report errors when duplicate labels are used, bug72.
|
2009-03-23 14:57:15 -04:00 |
|
Wilson Snyder
|
ecb08b0cf3
|
Internals: V3Link uses new common func to make symbol table
|
2009-03-23 13:52:36 -04:00 |
|
Wilson Snyder
|
71bdfd9710
|
Fix ASSIGN_SI errors with new --pins-bv 1 option
|
2009-03-13 22:58:55 -04:00 |
|
Wilson Snyder
|
193dcf38f4
|
Add --pins-bv option to use sc_bv for all ports.
|
2009-03-13 14:17:30 -04:00 |
|
Wilson Snyder
|
09091781cf
|
Fix the SC_MODULE name() to not include __PVT__, for nicer coverage.
|
2009-03-12 14:07:38 -04:00 |
|
Wilson Snyder
|
023519c8f6
|
Version bump
|
2009-02-26 07:44:00 -05:00 |
|
Wilson Snyder
|
d60d0a60c7
|
Support repeat and forever statements.
|
2009-02-25 22:06:59 -05:00 |
|
Wilson Snyder
|
8fe0c3dd84
|
Commentary in parser to match Verilog-Perl
|
2009-02-25 17:16:51 -05:00 |
|
Wilson Snyder
|
85419f01a9
|
Fix left associativity for ?: operators.
|
2009-02-07 20:54:09 -05:00 |
|
Wilson Snyder
|
a199f4a849
|
Update Bison parser to track Verilog-Perl 3.110. No functional change
|
2009-01-28 15:27:41 -05:00 |
|
Wilson Snyder
|
290795a76b
|
Commentary
|
2009-01-28 14:28:55 -05:00 |
|
Wilson Snyder
|
c2cf2bc0ba
|
Commentary
|
2009-01-26 18:36:59 -05:00 |
|
Wilson Snyder
|
2224918730
|
Fix error messages to consistently go to stderr.
|
2009-01-26 07:57:59 -05:00 |
|
Wilson Snyder
|
c4e69daecd
|
Add IEEE grammar comments; sync with Verilator-Perl parser
|
2009-01-24 21:36:14 -05:00 |
|
Wilson Snyder
|
9162e68d82
|
Commentary
|
2009-01-24 21:35:08 -05:00 |
|
Wilson Snyder
|
08f736ae33
|
bisonpre: Reconsile Verilog-Perl and Verilator bisonpre
|
2009-01-24 16:44:03 -05:00 |
|
Wilson Snyder
|
81092edab4
|
Commentary
|
2009-01-21 16:59:42 -05:00 |
|
Wilson Snyder
|
21b5a4e9e4
|
Add --debugi-<srcfile> option.
|
2009-01-21 16:56:50 -05:00 |
|
Wilson Snyder
|
057928b079
|
Fix VL_RANDom to better randomize bits.
|
2009-01-21 13:52:51 -05:00 |
|
Wilson Snyder
|
4beaa45199
|
Clock_enable is past experimental; bug50.
|
2009-01-20 07:24:57 -05:00 |
|
Wilson Snyder
|
8f88fa45f1
|
Make grammer names more closely track IEEE. No functional change.
|
2009-01-15 13:58:43 -05:00 |
|
Wilson Snyder
|
13e8176884
|
Fix compile issues with GCC 4.3, bug47.
|
2009-01-09 11:28:50 -05:00 |
|
Wilson Snyder
|
aac0130613
|
Version bump
|
2009-01-08 10:52:37 -05:00 |
|
Wilson Snyder
|
0877f44cb5
|
Fix creating parameterized modules when no parameter values are changed.
|
2009-01-08 09:22:31 -05:00 |
|
Wilson Snyder
|
59159b4811
|
Clock gating optimization, currently disabled. Merge from branch
|
2009-01-07 09:37:59 -05:00 |
|
Wilson Snyder
|
12bd12e112
|
Support bufif0, bufif1, notif0, notif1
|
2009-01-06 11:57:25 -05:00 |
|