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Author SHA1 Message Date
Geza Lore
599d23697d
IEEE compliant scheduler (#3384) 
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
 2022-05-15 16:03:32 +01:00
Wilson Snyder
915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Wilson Snyder
3a5cbd5b67 Internals: Untabify some embedded tabs. 2021-11-13 10:46:25 -05:00
Julien Margetts
a11700271f
Add LATCH and NOLATCH warnings (#1609) (#2740). 2021-01-05 14:26:01 -05:00
Wilson Snyder
1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder
e57d004718 Fix clock-gates with non-AND complex logic, bug220. 2010-03-16 18:50:26 -04:00