Mario1159/verilator
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45aa8742d8
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138 Commits

Author SHA1 Message Date
Wilson Snyder
45aa8742d8 Internals: Rename implicit_typeE to match Verilog-Perl 2009-12-17 20:58:14 -05:00
Wilson Snyder
5a9309de78 DPI import: Allow system calls to call imports 2009-12-04 07:05:44 -05:00
Wilson Snyder
a40fae04ce Support direct programming interface (DPI) "import". 2009-12-03 06:55:29 -05:00
Wilson Snyder
1da07a3b86 Fix auto-indentation of AstCStmts 2009-12-01 21:55:56 -05:00
Wilson Snyder
955824e634 Fix functions arguments without leading input 2009-11-24 22:16:28 -05:00
Wilson Snyder
d2a27a84cf Support chandle 2009-11-24 09:11:25 -05:00
Wilson Snyder
c7d8eb126f Support and . 2009-11-23 21:24:55 -05:00
Wilson Snyder
2f2f367c0b Internals: AstConst named functions when want true/false size 1 2009-11-22 20:05:33 -05:00
Wilson Snyder
d7a2362a76 Parse UDP Tables, and report single unsupported error 2009-11-20 19:53:40 -05:00
Wilson Snyder
e479c8a553 Support 'primitive', but not yet 'table'. 2009-11-20 08:41:28 -05:00
Wilson Snyder
62f707f501 Support $test$plusargs and $value$plusargs, but see the docs. 2009-11-19 17:04:21 -05:00
Wilson Snyder
19d62b7a68 Support 'time'. 2009-11-19 10:45:59 -05:00
Wilson Snyder
92819f5082 Fix multi-dimensional arrayed typedefs, bug183. 2009-11-12 20:50:31 -05:00
Wilson Snyder
736b9074c8 Support for loop i++, ++i, i--, --i, bug175. 2009-11-10 16:40:07 -05:00
Wilson Snyder
376147911f Support optional cell parenthesis, bug179 2009-11-10 16:29:58 -05:00
Wilson Snyder
67d1dad77c Support declarations in loop initializers, bug172. 2009-11-09 19:09:27 -05:00
Wilson Snyder
3b39c3391d Support "import". 2009-11-09 19:07:59 -05:00
Wilson Snyder
68567e763c Support "package" and $unit. 
Add VARHIDDEN warning when signal name hides module name.
 2009-11-07 21:05:02 -05:00
Wilson Snyder
377f194837 Support typedef 2009-11-06 23:16:06 -05:00
Wilson Snyder
b1ce6bd5cc Support "var" 2009-11-05 19:57:31 -05:00
Wilson Snyder
81915540de Support "reg x [3][2]". 2009-11-05 19:26:44 -05:00
Wilson Snyder
0d65f08b1d Support "program". 2009-11-05 19:09:45 -05:00
Wilson Snyder
ffbd1fd474 Support "reg [1:0][1:0][1:0]", bug176. 2009-11-05 09:57:23 -05:00
Wilson Snyder
700c1f836d Internals: Move array definitions to AstArrayDType instead of under AstVars. 
Prep work for more complicated data types.
 2009-11-04 22:31:53 -05:00
Wilson Snyder
f59467b897 Support void functions. 
Fix "int" etc added in wrong keyword section in last commit.
 2009-11-02 22:50:31 -05:00
Wilson Snyder
6bc81d3d26 Support byte, shortint, int, longint in variables, parameters and functions. 
Internals: function/var sizing and signing now comes via dtypep()
Internals: cleanup code that widths parameters (again)
 2009-11-02 22:14:11 -05:00
Wilson Snyder
4c26792c9b Internals: Create data types and attach to AstVars, in prep for typedefs. 
Added AstNodeDType and AstBasicDType and associated enums.
 2009-11-02 08:06:04 -05:00
Wilson Snyder
9a133ced2d Support 'bit' keyword 2009-10-31 15:12:28 -04:00
Wilson Snyder
18bebaf5c3 Internals: Add parse-time symbol table for eventual typedef detection 2009-10-31 10:26:53 -04:00
Wilson Snyder
f7efae93d5 Internals: Clean up the main flex/bison files to have some sanity. 
(Hopefully) no functional change.
	. V3Parse.h		External consumer interface to V3ParseImp
	. V3ParseImp		Internals to parser, common to across flex & bison
	... V3ParseGrammar	Wrapper that includes V3ParseBison
	..... V3ParseBison	Bison output
	... V3ParseLex		Wrapper that includes lex output
	..... V3Lexer.yy.cpp	Flex output
 2009-10-31 10:08:38 -04:00
Wilson Snyder
7b4d2118ea Internals: Realign flex with Verilog-Perl version 2009-10-30 23:17:56 -04:00
Wilson Snyder
b4d3806f10 Fix carriage-returns embedded in display formats 
Internals: Store all AstDisplay etc strings in un-backslashed raw format.
 2009-10-22 21:29:18 -04:00
Wilson Snyder
b1e6fe7139 Fix core dump with SystemVerilog var declarations under unnamed begins. 2009-10-11 20:50:31 -04:00
Wilson Snyder
7069d7d802 Internals: Remove AstAssignW::allowImplicit - dead code 2009-10-06 21:58:00 -04:00
Wilson Snyder
0c0a588b55 Support generate for var++, var--, ++var, --var. 2009-09-16 10:32:14 -04:00
Wilson Snyder
faa5ef193b Add --bbox-sys option to blackbox $system calls. 2009-09-16 09:28:09 -04:00
Wilson Snyder
eea2712eac Improved warning when "do" used as identifier. 2009-09-07 15:54:12 -04:00
Wilson Snyder
4dde1ede0e Support SystemVerilog "logic", bug101. 2009-07-16 09:19:15 -04:00
Wilson Snyder
0a02d1f336 Reconsile with Verilog-Perl r77464 2009-05-19 07:49:19 -04:00
Wilson Snyder
f9484a894f Reconsile with Verilog-Perl 2009-05-11 20:32:52 -04:00
Wilson Snyder
4569278c53 Reconsile parser with Verilog-Perl version, to enable more SV features 2009-05-07 18:28:05 -04:00
Wilson Snyder
851b022c7a Change lexer to more closely match Verilog-Perl. Should be no functional change 2009-05-05 13:39:25 -04:00
Wilson Snyder
0985f675e3 Update bisonpre to match Verilog-Perl version 2009-05-04 21:54:44 -04:00
Wilson Snyder
7df730cedd Verilator is now licensed under LGPL v3 and/or Artistic v2.0. 2009-05-04 17:07:57 -04:00
Wilson Snyder
d60d0a60c7 Support repeat and forever statements. 2009-02-25 22:06:59 -05:00
Wilson Snyder
8fe0c3dd84 Commentary in parser to match Verilog-Perl 2009-02-25 17:16:51 -05:00
Wilson Snyder
85419f01a9 Fix left associativity for ?: operators. 2009-02-07 20:54:09 -05:00
Wilson Snyder
a199f4a849 Update Bison parser to track Verilog-Perl 3.110. No functional change 2009-01-28 15:27:41 -05:00
Wilson Snyder
c4e69daecd Add IEEE grammar comments; sync with Verilator-Perl parser 2009-01-24 21:36:14 -05:00
Wilson Snyder
8f88fa45f1 Make grammer names more closely track IEEE. No functional change. 2009-01-15 13:58:43 -05:00