forked from github/verilator
Reconsile with Verilog-Perl
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@ -1312,11 +1312,11 @@ cellpinItList<pinp>: // IEEE: list_of_port_connections + list_of_parameter_assi
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cellpinItemE<pinp>: // IEEE: named_port_connection + named_parameter_assignment + empty
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/* empty: ',,' is legal */ { $$ = NULL; PINNUMINC(); }
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| yP_DOTSTAR { $$ = new AstPin($1,PINNUMINC(),".*",NULL); }
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| '.' id { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
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| '.' id '(' ')' { $$ = NULL; PINNUMINC(); }
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| '.' id '(' expr ')' { $$ = new AstPin($1,PINNUMINC(),*$2,$4); }
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| '.' idAny { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
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| '.' idAny '(' ')' { $$ = NULL; PINNUMINC(); }
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| '.' idAny '(' expr ')' { $$ = new AstPin($1,PINNUMINC(),*$2,$4); }
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// // For parameters
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//UNSUP '.' id '(' data_type ')' { PINDONE($1,$2,$4); GRAMMARP->pinNumInc(); }
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//UNSUP '.' idAny '(' data_type ')' { PINDONE($1,$2,$4); GRAMMARP->pinNumInc(); }
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// // For parameters
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//UNSUP data_type { PINDONE($1->fileline(),"",$1); GRAMMARP->pinNumInc(); }
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//
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