forked from github/verilator
bug951 testcase
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test_regress/t/t_bitsel_enum.pl
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20
test_regress/t/t_bitsel_enum.pl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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$Self->skip("Not supported by commercial simulators");
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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test_regress/t/t_bitsel_enum.v
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test_regress/t/t_bitsel_enum.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Jonathon Donaldson.
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module t_bitsel_enum
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(
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output out0,
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output out1
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);
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localparam [6:0] CNST_VAL = 7'h22;
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enum logic [6:0] {
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ENUM_VAL = 7'h33
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} MyEnum;
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assign out0 = CNST_VAL[0];
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// This is not supported by NC-verilog nor VCS, so Verilator does not support it either
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assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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