From ff9f5b62ac9f95c3c5dd4c8d9178a6fded9c40f7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 12 Aug 2015 08:36:23 -0400 Subject: [PATCH] bug951 testcase --- test_regress/t/t_bitsel_enum.pl | 20 ++++++++++++++++++++ test_regress/t/t_bitsel_enum.v | 27 +++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100755 test_regress/t/t_bitsel_enum.pl create mode 100644 test_regress/t/t_bitsel_enum.v diff --git a/test_regress/t/t_bitsel_enum.pl b/test_regress/t/t_bitsel_enum.pl new file mode 100755 index 000000000..de004ca71 --- /dev/null +++ b/test_regress/t/t_bitsel_enum.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->skip("Not supported by commercial simulators"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_bitsel_enum.v b/test_regress/t/t_bitsel_enum.v new file mode 100644 index 000000000..3143dc2ad --- /dev/null +++ b/test_regress/t/t_bitsel_enum.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jonathon Donaldson. + +module t_bitsel_enum + ( + output out0, + output out1 + ); + + localparam [6:0] CNST_VAL = 7'h22; + + enum logic [6:0] { + ENUM_VAL = 7'h33 + } MyEnum; + + assign out0 = CNST_VAL[0]; + // This is not supported by NC-verilog nor VCS, so Verilator does not support it either + assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule