Fix disable iff in assertions. Closes #1404.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>

Changes

@@ -26,6 +26,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix strcasecmp for windows, #1651. [Kuba Ober]
 
+****  Fix disable iff in assertions. Closes #1404. [Peter Monsson]
+
 
 * Verilator 4.024 2019-12-08
 

docs/CONTRIBUTORS

@@ -24,6 +24,7 @@ Lukasz Dalek
 Maarten De Braekeleer
 Matthew Ballance
 Mike Popoloski
+Peter Monsson
 Patrick Stewart
 Philipp Wagner
 Richard Myers

src/V3AssertPre.cpp

@@ -116,10 +116,16 @@ private:
         // Block is the new expression to evaluate
         AstNode* blockp = nodep->propp()->unlinkFrBack();
         if (nodep->disablep()) {
-            blockp = new AstAnd(nodep->disablep()->fileline(),
-                                new AstNot(nodep->disablep()->fileline(),
-                                           nodep->disablep()->unlinkFrBack()),
-                                blockp);
+            if (VN_IS(nodep->backp(), Cover)) {
+                blockp = new AstAnd(nodep->disablep()->fileline(),
+                                    new AstNot(nodep->disablep()->fileline(),
+                                               nodep->disablep()->unlinkFrBack()),
+                                    blockp);
+            } else {
+                blockp = new AstOr(nodep->disablep()->fileline(),
+                                   nodep->disablep()->unlinkFrBack(),
+                                   blockp);
+            }
         }
         // Unlink and just keep a pointer to it, convert to sentree as needed
         m_senip = nodep->sensesp();

test_regress/t/t_assert_disable_iff.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert --cc --coverage-user'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_disable_iff.v

@@ -0,0 +1,81 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Peter Monsson.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   Test test (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk));
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+         cyc <= cyc + 1;
+         if (cyc==10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+endmodule
+
+module Test
+  (
+   input clk
+   );
+
+`ifdef FAIL_ASSERT_1
+   assert property (
+     @(posedge clk) disable iff (0)
+     0
+   ) else $display("wrong disable");
+`endif
+
+   assert property (
+     @(posedge clk) disable iff (1)
+     0
+   );
+
+   assert property (
+     @(posedge clk) disable iff (1)
+     1
+   );
+
+   assert property (
+     @(posedge clk) disable iff (0)
+     1
+   );
+
+   //
+   // Cover properties behave differently
+   //
+
+   cover property (
+     @(posedge clk) disable iff (1)
+     1
+   ) $stop;
+
+   cover property (
+     @(posedge clk) disable iff (1)
+     0
+   ) $stop;
+
+   cover property (
+     @(posedge clk) disable iff (0)
+     1
+   ) $display("*COVER: ok");
+
+   cover property (
+     @(posedge clk) disable iff (0)
+     0
+   ) $stop;
+
+endmodule