From ea979c8f83f655bba388a449cb2dee50856ae3eb Mon Sep 17 00:00:00 2001
From: Peter Monsson <>
Date: Sun, 22 Dec 2019 15:49:10 -0500
Subject: [PATCH] Fix disable iff in assertions. Closes #1404.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
---
 Changes                                |  2 +
 docs/CONTRIBUTORS                      |  1 +
 src/V3AssertPre.cpp                    | 14 +++--
 test_regress/t/t_assert_disable_iff.pl | 21 +++++++
 test_regress/t/t_assert_disable_iff.v  | 81 ++++++++++++++++++++++++++
 5 files changed, 115 insertions(+), 4 deletions(-)
 create mode 100644 test_regress/t/t_assert_disable_iff.pl
 create mode 100644 test_regress/t/t_assert_disable_iff.v

diff --git a/Changes b/Changes
index 29a4012bd..2b0bb2d6f 100644
--- a/Changes
+++ b/Changes
@@ -26,6 +26,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix strcasecmp for windows, #1651. [Kuba Ober]
 
+****  Fix disable iff in assertions. Closes #1404. [Peter Monsson]
+
 
 * Verilator 4.024 2019-12-08
 
diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index ed7fd6b52..ab88d1a58 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -24,6 +24,7 @@ Lukasz Dalek
 Maarten De Braekeleer
 Matthew Ballance
 Mike Popoloski
+Peter Monsson
 Patrick Stewart
 Philipp Wagner
 Richard Myers
diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index 9916635aa..bc4f6bfd9 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -116,10 +116,16 @@ private:
         // Block is the new expression to evaluate
         AstNode* blockp = nodep->propp()->unlinkFrBack();
         if (nodep->disablep()) {
-            blockp = new AstAnd(nodep->disablep()->fileline(),
-                                new AstNot(nodep->disablep()->fileline(),
-                                           nodep->disablep()->unlinkFrBack()),
-                                blockp);
+            if (VN_IS(nodep->backp(), Cover)) {
+                blockp = new AstAnd(nodep->disablep()->fileline(),
+                                    new AstNot(nodep->disablep()->fileline(),
+                                               nodep->disablep()->unlinkFrBack()),
+                                    blockp);
+            } else {
+                blockp = new AstOr(nodep->disablep()->fileline(),
+                                   nodep->disablep()->unlinkFrBack(),
+                                   blockp);
+            }
         }
         // Unlink and just keep a pointer to it, convert to sentree as needed
         m_senip = nodep->sensesp();
diff --git a/test_regress/t/t_assert_disable_iff.pl b/test_regress/t/t_assert_disable_iff.pl
new file mode 100644
index 000000000..90b4e1666
--- /dev/null
+++ b/test_regress/t/t_assert_disable_iff.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert --cc --coverage-user'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_disable_iff.v b/test_regress/t/t_assert_disable_iff.v
new file mode 100644
index 000000000..7e07d0184
--- /dev/null
+++ b/test_regress/t/t_assert_disable_iff.v
@@ -0,0 +1,81 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Peter Monsson.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   Test test (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk));
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+         cyc <= cyc + 1;
+         if (cyc==10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+endmodule
+
+module Test
+  (
+   input clk
+   );
+
+`ifdef FAIL_ASSERT_1
+   assert property (
+     @(posedge clk) disable iff (0)
+     0
+   ) else $display("wrong disable");
+`endif
+
+   assert property (
+     @(posedge clk) disable iff (1)
+     0
+   );
+
+   assert property (
+     @(posedge clk) disable iff (1)
+     1
+   );
+
+   assert property (
+     @(posedge clk) disable iff (0)
+     1
+   );
+
+   //
+   // Cover properties behave differently
+   //
+
+   cover property (
+     @(posedge clk) disable iff (1)
+     1
+   ) $stop;
+
+   cover property (
+     @(posedge clk) disable iff (1)
+     0
+   ) $stop;
+
+   cover property (
+     @(posedge clk) disable iff (0)
+     1
+   ) $display("*COVER: ok");
+
+   cover property (
+     @(posedge clk) disable iff (0)
+     0
+   ) $stop;
+
+endmodule