Tests: Add defparam not resolved test

This commit is contained in:
Wilson Snyder 2023-02-11 11:00:07 -05:00
parent 4d29487e75
commit dee2e45e27
4 changed files with 37 additions and 1 deletions

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@ -57,7 +57,6 @@ foreach my $s (
'Illegal +: or -: select; type already selected, or bad dimension: ',
'Illegal bit or array select; type already selected, or bad dimension: ',
'Illegal range select; type already selected, or bad dimension: ',
'In defparam, instance ',
'Interface port ',
'Member selection of non-struct/union object \'',
'Modport item is not a function/task: ',

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@ -0,0 +1,4 @@
%Error: t/t_gen_defparam_nfound_bad.v:9:17: In defparam, instance z never declared
9 | defparam z.W = 3;
| ^
%Error: Exiting due to

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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
a a ();
defparam z.W = 3; // Bad
endmodule
module a;
parameter W = 0;
endmodule