diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl
index 258b74a8f..febbe85c2 100755
--- a/test_regress/t/t_dist_warn_coverage.pl
+++ b/test_regress/t/t_dist_warn_coverage.pl
@@ -57,7 +57,6 @@ foreach my $s (
     'Illegal +: or -: select; type already selected, or bad dimension: ',
     'Illegal bit or array select; type already selected, or bad dimension: ',
     'Illegal range select; type already selected, or bad dimension: ',
-    'In defparam, instance ',
     'Interface port ',
     'Member selection of non-struct/union object \'',
     'Modport item is not a function/task: ',
diff --git a/test_regress/t/t_gen_defparam_nfound_bad.out b/test_regress/t/t_gen_defparam_nfound_bad.out
new file mode 100644
index 000000000..b66fe1bd3
--- /dev/null
+++ b/test_regress/t/t_gen_defparam_nfound_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_gen_defparam_nfound_bad.v:9:17: In defparam, instance z never declared
+    9 |    defparam z.W = 3;   
+      |                 ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_gen_defparam_nfound_bad.pl b/test_regress/t/t_gen_defparam_nfound_bad.pl
new file mode 100755
index 000000000..a5846c699
--- /dev/null
+++ b/test_regress/t/t_gen_defparam_nfound_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_defparam_nfound_bad.v b/test_regress/t/t_gen_defparam_nfound_bad.v
new file mode 100644
index 000000000..85c1017c6
--- /dev/null
+++ b/test_regress/t/t_gen_defparam_nfound_bad.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   a a ();
+   defparam z.W = 3;  // Bad
+endmodule
+
+module a;
+   parameter W = 0;
+endmodule