forked from github/verilator
Support $error/$warning in elaboration time blocks.
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2
Changes
@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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*** Support self-recursive modules, bug659. [Sean Moore, et al]
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*** Support $error/$warning in elaboration time blocks.
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**** Fix MacOS portability, bug1232. [Jeff Bush]
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**** Detect MSB overflow when under VL_DEBUG, bug1238. [Junyi Xi]
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@ -1074,7 +1074,7 @@ program_generate_item<nodep>: // ==IEEE: program_generate_item
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loop_generate_construct { $$ = $1; }
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| conditional_generate_construct { $$ = $1; }
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| generate_region { $$ = $1; }
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//UNSUP elaboration_system_task { $$ = $1; }
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| elaboration_system_task { $$ = $1; }
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;
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modport_declaration<nodep>: // ==IEEE: modport_declaration
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@ -1722,6 +1722,7 @@ module_common_item<nodep>: // ==IEEE: module_common_item
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| yALWAYS_LATCH event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_LATCH, $2,$3); }
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| loop_generate_construct { $$ = $1; }
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| conditional_generate_construct { $$ = $1; }
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| elaboration_system_task { $$ = $1; }
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//
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| error ';' { $$ = NULL; }
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;
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@ -2738,6 +2739,24 @@ system_f_call<nodep>: // IEEE: system_tf_call (as func)
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| yD_VALUEPLUSARGS '(' expr ',' expr ')' { $$ = new AstValuePlusArgs($1,$3,$5); }
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;
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elaboration_system_task<nodep>: // IEEE: elaboration_system_task (1800-2009)
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// // TODO: These currently just make initial statements, should instead give runtime error
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elaboration_system_task_guts ';' { $$ = new AstInitial($<fl>1, $1); }
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;
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elaboration_system_task_guts<nodep>: // IEEE: part of elaboration_system_task (1800-2009)
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// // $fatal first argument is exit number, must be constant
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yD_INFO parenE { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, "", NULL,NULL); }
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| yD_INFO '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, *$3,NULL,$4); }
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| yD_WARNING parenE { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING,"", NULL,NULL); }
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| yD_WARNING '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING,*$3,NULL,$4); }
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| yD_ERROR parenE { $$ = GRAMMARP->createDisplayError($1); }
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| yD_ERROR '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_ERROR, *$3,NULL,$4); $$->addNext(new AstStop($1)); }
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| yD_FATAL parenE { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, "", NULL,NULL); $$->addNext(new AstStop($1)); }
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| yD_FATAL '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, "", NULL,NULL); $$->addNext(new AstStop($1)); DEL($3); }
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| yD_FATAL '(' expr ',' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, *$5,NULL,$6); $$->addNext(new AstStop($1)); DEL($3); }
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;
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exprOrDataType<nodep>: // expr | data_type: combined to prevent conflicts
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expr { $$ = $1; }
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// // data_type includes id that overlaps expr, so special flavor
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20
test_regress/t/t_assert_comp.pl
Executable file
20
test_regress/t/t_assert_comp.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ['--assert'],
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nc_flags2 => ['+assert'],
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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17
test_regress/t/t_assert_comp.v
Normal file
17
test_regress/t/t_assert_comp.v
Normal file
@ -0,0 +1,17 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/);
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if (0) begin
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$warning("User compile-time warning");
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$error("User compile-time error");
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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25
test_regress/t/t_assert_comp_bad.pl
Executable file
25
test_regress/t/t_assert_comp_bad.pl
Executable file
@ -0,0 +1,25 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ['--assert'],
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nc_flags2 => ['+assert'],
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);
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execute (
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check_finished=>0,
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fails => 1,
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expect =>
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'.*%Warning: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time warning
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.*%Error: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time error'
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);
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ok(1);
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1;
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13
test_regress/t/t_assert_comp_bad.v
Normal file
13
test_regress/t/t_assert_comp_bad.v
Normal file
@ -0,0 +1,13 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/);
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if (1) begin
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$warning("User compile-time warning");
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$error("User compile-time error");
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end
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endmodule
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