From dd37c2ea867737d0b15c211ac94bbcacd64616f9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 21 Nov 2017 21:10:42 -0500 Subject: [PATCH] Support $error/$warning in elaboration time blocks. --- Changes | 2 ++ src/verilog.y | 21 ++++++++++++++++++++- test_regress/t/t_assert_comp.pl | 20 ++++++++++++++++++++ test_regress/t/t_assert_comp.v | 17 +++++++++++++++++ test_regress/t/t_assert_comp_bad.pl | 25 +++++++++++++++++++++++++ test_regress/t/t_assert_comp_bad.v | 13 +++++++++++++ 6 files changed, 97 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_assert_comp.pl create mode 100644 test_regress/t/t_assert_comp.v create mode 100755 test_regress/t/t_assert_comp_bad.pl create mode 100644 test_regress/t/t_assert_comp_bad.v diff --git a/Changes b/Changes index 529be4b95..bbf358e1d 100644 --- a/Changes +++ b/Changes @@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks! *** Support self-recursive modules, bug659. [Sean Moore, et al] +*** Support $error/$warning in elaboration time blocks. + **** Fix MacOS portability, bug1232. [Jeff Bush] **** Detect MSB overflow when under VL_DEBUG, bug1238. [Junyi Xi] diff --git a/src/verilog.y b/src/verilog.y index 95822da31..d32ee4483 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1074,7 +1074,7 @@ program_generate_item: // ==IEEE: program_generate_item loop_generate_construct { $$ = $1; } | conditional_generate_construct { $$ = $1; } | generate_region { $$ = $1; } - //UNSUP elaboration_system_task { $$ = $1; } + | elaboration_system_task { $$ = $1; } ; modport_declaration: // ==IEEE: modport_declaration @@ -1722,6 +1722,7 @@ module_common_item: // ==IEEE: module_common_item | yALWAYS_LATCH event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_LATCH, $2,$3); } | loop_generate_construct { $$ = $1; } | conditional_generate_construct { $$ = $1; } + | elaboration_system_task { $$ = $1; } // | error ';' { $$ = NULL; } ; @@ -2738,6 +2739,24 @@ system_f_call: // IEEE: system_tf_call (as func) | yD_VALUEPLUSARGS '(' expr ',' expr ')' { $$ = new AstValuePlusArgs($1,$3,$5); } ; +elaboration_system_task: // IEEE: elaboration_system_task (1800-2009) + // // TODO: These currently just make initial statements, should instead give runtime error + elaboration_system_task_guts ';' { $$ = new AstInitial($1, $1); } + ; + +elaboration_system_task_guts: // IEEE: part of elaboration_system_task (1800-2009) + // // $fatal first argument is exit number, must be constant + yD_INFO parenE { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, "", NULL,NULL); } + | yD_INFO '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_INFO, *$3,NULL,$4); } + | yD_WARNING parenE { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING,"", NULL,NULL); } + | yD_WARNING '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_WARNING,*$3,NULL,$4); } + | yD_ERROR parenE { $$ = GRAMMARP->createDisplayError($1); } + | yD_ERROR '(' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_ERROR, *$3,NULL,$4); $$->addNext(new AstStop($1)); } + | yD_FATAL parenE { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, "", NULL,NULL); $$->addNext(new AstStop($1)); } + | yD_FATAL '(' expr ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, "", NULL,NULL); $$->addNext(new AstStop($1)); DEL($3); } + | yD_FATAL '(' expr ',' str commaEListE ')' { $$ = new AstDisplay($1,AstDisplayType::DT_FATAL, *$5,NULL,$6); $$->addNext(new AstStop($1)); DEL($3); } + ; + exprOrDataType: // expr | data_type: combined to prevent conflicts expr { $$ = $1; } // // data_type includes id that overlaps expr, so special flavor diff --git a/test_regress/t/t_assert_comp.pl b/test_regress/t/t_assert_comp.pl new file mode 100755 index 000000000..4eada89db --- /dev/null +++ b/test_regress/t/t_assert_comp.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + verilator_flags2 => ['--assert'], + nc_flags2 => ['+assert'], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_comp.v b/test_regress/t/t_assert_comp.v new file mode 100644 index 000000000..4c4941f5b --- /dev/null +++ b/test_regress/t/t_assert_comp.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + if (0) begin + $warning("User compile-time warning"); + $error("User compile-time error"); + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl new file mode 100755 index 000000000..5733a2bcc --- /dev/null +++ b/test_regress/t/t_assert_comp_bad.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + verilator_flags2 => ['--assert'], + nc_flags2 => ['+assert'], + ); + +execute ( + check_finished=>0, + fails => 1, + expect => +'.*%Warning: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time warning +.*%Error: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time error' + + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v new file mode 100644 index 000000000..59229bc89 --- /dev/null +++ b/test_regress/t/t_assert_comp_bad.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + if (1) begin + $warning("User compile-time warning"); + $error("User compile-time error"); + end + +endmodule