Fix === with some tristate constants (#3551).

docs/CONTRIBUTORS

@@ -99,6 +99,7 @@ Rafal Kapuscik
 Raynard Qiao
 Richard Myers
 Rupert Swarbrick
+Ryszard Rozak
 Samuel Riedel
 Sean Cross
 Sebastien Van Cauwenberghe

src/V3Tristate.cpp

@@ -937,7 +937,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             iterateChildren(nodep);
             UINFO(9, dbgState() << nodep << endl);
             // Constification always moves const to LHS
-            const AstConst* const constp = VN_CAST(nodep->lhsp(), Const);
+            AstConst* const constp = VN_CAST(nodep->lhsp(), Const);
             AstVarRef* const varrefp = VN_CAST(nodep->rhsp(), VarRef);  // Input variable
             if (constp && constp->user1p() && varrefp) {
                 // 3'b1z0 -> ((3'b101 == in__en) && (3'b100 == in))
@@ -960,6 +960,21 @@ class TristateVisitor final : public TristateBaseVisitor {
                 if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: ");
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
+            } else if (constp && nodep->rhsp()->user1p()) {
+                FileLine* const fl = nodep->fileline();
+                constp->unlinkFrBack();
+                AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+                AstNode* newp = new AstLogAnd{
+                    fl, new AstEq{fl, newAllZerosOrOnes(constp, false), rhsp->user1p()},
+                    // Keep the caseeq if there are X's present
+                    new AstEqCase{fl, constp, rhsp}};
+                if (neq) newp = new AstLogNot{fl, newp};
+                rhsp->user1p(nullptr);
+                UINFO(9, "       newceq " << newp << endl);
+                if (debug() >= 9) nodep->dumpTree(cout, "-caseeq-old: ");
+                if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: ");
+                nodep->replaceWith(newp);
+                VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else {
                 checkUnhandled(nodep);
             }

test_regress/t/t_tri_cond_eqcase_with_1.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_cond_eqcase_with_1.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   wire  a;
+   assign a = 1 === (clk ? 1 : 1'bz);
+
+   always begin
+      if (!a) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

test_regress/t/t_tri_eqcase_input.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_eqcase_input.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   wire a = 1'bz === clk;
+
+   always begin
+      if (a) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule