From db5fdfb0ee871e4cf8a25b8890207b507d5fa7c9 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Thu, 18 Aug 2022 13:03:05 +0200 Subject: [PATCH] Fix === with some tristate constants (#3551). --- docs/CONTRIBUTORS | 1 + src/V3Tristate.cpp | 17 ++++++++++++++++- test_regress/t/t_tri_cond_eqcase_with_1.pl | 21 +++++++++++++++++++++ test_regress/t/t_tri_cond_eqcase_with_1.v | 21 +++++++++++++++++++++ test_regress/t/t_tri_eqcase_input.pl | 21 +++++++++++++++++++++ test_regress/t/t_tri_eqcase_input.v | 20 ++++++++++++++++++++ 6 files changed, 100 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_tri_cond_eqcase_with_1.pl create mode 100644 test_regress/t/t_tri_cond_eqcase_with_1.v create mode 100755 test_regress/t/t_tri_eqcase_input.pl create mode 100644 test_regress/t/t_tri_eqcase_input.v diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 0b003034b..228787d5e 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -99,6 +99,7 @@ Rafal Kapuscik Raynard Qiao Richard Myers Rupert Swarbrick +Ryszard Rozak Samuel Riedel Sean Cross Sebastien Van Cauwenberghe diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 20861faa9..21abe682c 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -937,7 +937,7 @@ class TristateVisitor final : public TristateBaseVisitor { iterateChildren(nodep); UINFO(9, dbgState() << nodep << endl); // Constification always moves const to LHS - const AstConst* const constp = VN_CAST(nodep->lhsp(), Const); + AstConst* const constp = VN_CAST(nodep->lhsp(), Const); AstVarRef* const varrefp = VN_CAST(nodep->rhsp(), VarRef); // Input variable if (constp && constp->user1p() && varrefp) { // 3'b1z0 -> ((3'b101 == in__en) && (3'b100 == in)) @@ -960,6 +960,21 @@ class TristateVisitor final : public TristateBaseVisitor { if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: "); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); + } else if (constp && nodep->rhsp()->user1p()) { + FileLine* const fl = nodep->fileline(); + constp->unlinkFrBack(); + AstNode* const rhsp = nodep->rhsp()->unlinkFrBack(); + AstNode* newp = new AstLogAnd{ + fl, new AstEq{fl, newAllZerosOrOnes(constp, false), rhsp->user1p()}, + // Keep the caseeq if there are X's present + new AstEqCase{fl, constp, rhsp}}; + if (neq) newp = new AstLogNot{fl, newp}; + rhsp->user1p(nullptr); + UINFO(9, " newceq " << newp << endl); + if (debug() >= 9) nodep->dumpTree(cout, "-caseeq-old: "); + if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: "); + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } else { checkUnhandled(nodep); } diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.pl b/test_regress/t/t_tri_cond_eqcase_with_1.pl new file mode 100755 index 000000000..f5e338520 --- /dev/null +++ b/test_regress/t/t_tri_cond_eqcase_with_1.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Antmicro Ltd. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.v b/test_regress/t/t_tri_cond_eqcase_with_1.v new file mode 100644 index 000000000..552280b98 --- /dev/null +++ b/test_regress/t/t_tri_cond_eqcase_with_1.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire a; + assign a = 1 === (clk ? 1 : 1'bz); + + always begin + if (!a) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_tri_eqcase_input.pl b/test_regress/t/t_tri_eqcase_input.pl new file mode 100755 index 000000000..f5e338520 --- /dev/null +++ b/test_regress/t/t_tri_eqcase_input.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Antmicro Ltd. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_tri_eqcase_input.v b/test_regress/t/t_tri_eqcase_input.v new file mode 100644 index 000000000..518ae40e1 --- /dev/null +++ b/test_regress/t/t_tri_eqcase_input.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire a = 1'bz === clk; + + always begin + if (a) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule