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Tests: Add VERILATOR_MAKE override variable.

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This commit is contained in:
Wilson Snyder 2018-10-30 20:28:39 -04:00
parent 14b48140bd
commit d3e1dfd3f5
1 changed files with 7 additions and 2 deletions
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9
test_regress/driver.pl
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@ -187,8 +187,9 @@ sub one_test {
} else {
$test->oprint("FAILED: ","*"x60,"\n");
my $j = ($opt_jobs>1?" -j":"");
push @fails, ("\t#".$test->soprint("%Error: $test->{errors}\n")
."\t\tmake$j && test_regress/"
my $makecmd = $ENV{VERILATOR_MAKE} || "make$j &&";
push @fails, ("\t#".$test->soprint("%Error: $test->{errors}\n")
."\t\t$makecmd test_regress/"
.$test->{pl_filename}
." ".join(' ', _args_scenario())
." --".$test->{scenario}."\n");
@ -2143,6 +2144,10 @@ Command to use to invoke GHDL.
Command to use to invoke Icarus Verilog.
=item VERILATOR_MAKE
Command to use to rebuild Verilator and run single test. Defaults to "make &&".
=item VERILATOR_MODELSIM
Command to use to invoke ModelSim.