Mario1159/verilator
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In --xml-only show the original unmodified names, msg2716.

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Wilson Snyder 2018-10-30 18:17:37 -04:00
parent 7be1678fb0
commit 14b48140bd
4 changed files with 29 additions and 20 deletions
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@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 4.007 devel
*** In --xml-only show the original unmodified names, msg2716. [Kanad Kanhere]
**** Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]

7
src/V3EmitXml.cpp
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@ -99,6 +99,7 @@ class EmitXmlFileVisitor : public AstNVisitor {
virtual void visit(AstCell* nodep) {
outputTag(nodep, "instance"); // IEEE: vpiInstance
puts(" defName="); putsQuoted(nodep->modName()); // IEEE vpiDefName
puts(" origName="); putsQuoted(nodep->origName());
outputChildrenEnd(nodep, "instance");
}
virtual void visit(AstNetlist* nodep) {
@ -108,10 +109,16 @@ class EmitXmlFileVisitor : public AstNVisitor {
}
virtual void visit(AstNodeModule* nodep) {
outputTag(nodep, "");
puts(" origName="); putsQuoted(nodep->origName());
if (nodep->level()==1 || nodep->level()==2) // ==2 because we don't add wrapper when in XML mode
puts(" topModule=\"1\""); // IEEE vpiTopModule
outputChildrenEnd(nodep, "");
}
virtual void visit(AstVar* nodep) {
outputTag(nodep, "");
puts(" origName="); putsQuoted(nodep->origName());
outputChildrenEnd(nodep, "");
}
virtual void visit(AstPin* nodep) {
// What we call a pin in verilator is a port in the IEEE spec.
outputTag(nodep, "port"); // IEEE: vpiPort

30
test_regress/t/t_xml_first.out
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@ -10,12 +10,12 @@
<file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
</files>
<netlist>
<module fl="f6" name="t" topModule="1">
<var fl="f12" name="clk" dtype_id="1"/>
<var fl="f13" name="d" dtype_id="2"/>
<var fl="f14" name="q" dtype_id="2"/>
<var fl="f16" name="between" dtype_id="2"/>
<instance fl="f18" name="cell1" defName="mod1">
<module fl="f6" name="t" origName="t" topModule="1">
<var fl="f12" name="clk" dtype_id="1" origName="clk"/>
<var fl="f13" name="d" dtype_id="2" origName="d"/>
<var fl="f14" name="q" dtype_id="2" origName="q"/>
<var fl="f16" name="between" dtype_id="2" origName="between"/>
<instance fl="f18" name="cell1" defName="mod1" origName="cell1">
<port fl="f18" name="q" direction="out" portIndex="1">
<varref fl="f18" name="between" dtype_id="2"/>
</port>
@ -26,7 +26,7 @@
<varref fl="f22" name="d" dtype_id="2"/>
</port>
</instance>
<instance fl="f24" name="cell2" defName="mod2">
<instance fl="f24" name="cell2" defName="mod2" origName="cell2">
<port fl="f24" name="d" direction="in" portIndex="1">
<varref fl="f24" name="between" dtype_id="2"/>
</port>
@ -38,10 +38,10 @@
</port>
</instance>
</module>
<module fl="f33" name="mod1">
<var fl="f35" name="clk" dtype_id="1"/>
<var fl="f36" name="d" dtype_id="2"/>
<var fl="f37" name="q" dtype_id="2"/>
<module fl="f33" name="mod1" origName="mod1">
<var fl="f35" name="clk" dtype_id="1" origName="clk"/>
<var fl="f36" name="d" dtype_id="2" origName="d"/>
<var fl="f37" name="q" dtype_id="2" origName="q"/>
<always fl="f39">
<sentree fl="f39">
<senitem fl="f39" edgeType="POS">
@ -54,10 +54,10 @@
</assigndly>
</always>
</module>
<module fl="f44" name="mod2">
<var fl="f46" name="clk" dtype_id="1"/>
<var fl="f47" name="d" dtype_id="2"/>
<var fl="f48" name="q" dtype_id="2"/>
<module fl="f44" name="mod2" origName="mod2">
<var fl="f46" name="clk" dtype_id="1" origName="clk"/>
<var fl="f47" name="d" dtype_id="2" origName="d"/>
<var fl="f48" name="q" dtype_id="2" origName="q"/>
<contassign fl="f51" dtype_id="2">
<varref fl="f51" name="d" dtype_id="2"/>
<varref fl="f51" name="q" dtype_id="2"/>

10
test_regress/t/t_xml_tag.out
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@ -10,12 +10,12 @@
<file id="f" filename="t/t_xml_tag.v" language="1800-2017"/>
</files>
<netlist>
<module fl="f6" name="m">
<var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1"/>
<var fl="f9" name="rst_ip" dtype_id="1"/>
<var fl="f10" name="foo_op" tag="foo_op" dtype_id="1"/>
<module fl="f6" name="m" origName="m">
<var fl="f8" name="clk_ip" tag="clk_ip" dtype_id="1" origName="clk_ip"/>
<var fl="f9" name="rst_ip" dtype_id="1" origName="rst_ip"/>
<var fl="f10" name="foo_op" tag="foo_op" dtype_id="1" origName="foo_op"/>
<typedef fl="f14" name="my_struct" tag="my_struct" dtype_id="2"/>
<var fl="f23" name="this_struct" tag="this_struct" dtype_id="3"/>
<var fl="f23" name="this_struct" tag="this_struct" dtype_id="3" origName="this_struct"/>
</module>
<typetable fl="a0">
<basicdtype fl="f23" id="4" name="logic" left="31" right="0"/>