diff --git a/docs/gen/ex_WIDTH_1_faulty.rst b/docs/gen/ex_WIDTHEXPAND_1_faulty.rst similarity index 75% rename from docs/gen/ex_WIDTH_1_faulty.rst rename to docs/gen/ex_WIDTHEXPAND_1_faulty.rst index 0121e66ac..08c1f0ba2 100644 --- a/docs/gen/ex_WIDTH_1_faulty.rst +++ b/docs/gen/ex_WIDTHEXPAND_1_faulty.rst @@ -1,4 +1,4 @@ -.. comment: generated by t_lint_width_docs_bad +.. comment: generated by t_lint_widthexpand_docs_bad .. code-block:: sv :linenos: :emphasize-lines: 3 diff --git a/docs/gen/ex_WIDTH_1_fixed.rst b/docs/gen/ex_WIDTHEXPAND_1_fixed.rst similarity index 66% rename from docs/gen/ex_WIDTH_1_fixed.rst rename to docs/gen/ex_WIDTHEXPAND_1_fixed.rst index 11a33b7d0..b40b8b2a6 100644 --- a/docs/gen/ex_WIDTH_1_fixed.rst +++ b/docs/gen/ex_WIDTHEXPAND_1_fixed.rst @@ -1,4 +1,4 @@ -.. comment: generated by t_lint_width_docs_bad +.. comment: generated by t_lint_widthexpand_docs_bad .. code-block:: sv :emphasize-lines: 1 diff --git a/docs/gen/ex_WIDTHEXPAND_1_msg.rst b/docs/gen/ex_WIDTHEXPAND_1_msg.rst new file mode 100644 index 000000000..927476284 --- /dev/null +++ b/docs/gen/ex_WIDTHEXPAND_1_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_lint_widthexpand_docs_bad +.. code-block:: + + %Warning-WIDTHEXPAND: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits. diff --git a/docs/gen/ex_WIDTH_1_msg.rst b/docs/gen/ex_WIDTH_1_msg.rst deleted file mode 100644 index 276a8ffc6..000000000 --- a/docs/gen/ex_WIDTH_1_msg.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. comment: generated by t_lint_width_docs_bad -.. code-block:: - - %Warning-WIDTH: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits. diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 7f0011153..d843f580b 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1790,16 +1790,27 @@ List Of Warnings For example, this is a missized index: - .. include:: ../../docs/gen/ex_WIDTH_1_faulty.rst + .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_faulty.rst - Results in: + Results in a WIDTHEXPAND warning: - .. include:: ../../docs/gen/ex_WIDTH_1_msg.rst + .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_msg.rst One possible fix: - .. include:: ../../docs/gen/ex_WIDTH_1_fixed.rst + .. include:: ../../docs/gen/ex_WIDTHEXPAND_1_fixed.rst +.. option:: WIDTHTRUNC + + A more granular WIDTH warning, for when a value is truncated + +.. option:: WIDTHEXPAND + + A more granular WIDTH warning, for when a value is zero expanded + +.. option:: WIDTHXZEXPAND + + A more granular WIDTH warning, for when a value is xz expanded .. option:: WIDTHCONCAT diff --git a/src/V3Config.cpp b/src/V3Config.cpp index f5018d8cc..b6ede32c0 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -332,8 +332,7 @@ public: } bool waive(V3ErrorCode code, const string& match) { for (const auto& itr : m_waivers) { - if (((itr.first == code) || (itr.first == V3ErrorCode::I_LINT) - || (code.unusedError() && itr.first == V3ErrorCode::I_UNUSED)) + if ((code.isUnder(itr.first) || (itr.first == V3ErrorCode::I_LINT)) && VString::wildmatch(match, itr.second)) { return true; } diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index 885392513..29ec3e422 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -262,7 +262,7 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const } if (argp->widthMin() > 8 && fmtLetter == 'c') { // Technically legal, but surely not what the user intended. - argp->v3warn(WIDTH, dispp->verilogKwd() << "of %c format of > 8 bit value"); + argp->v3warn(WIDTHTRUNC, dispp->verilogKwd() << "of %c format of > 8 bit value"); } } // string pfmt = "%"+displayFormat(argp, vfmt, fmtLetter)+fmtLetter; diff --git a/src/V3Error.h b/src/V3Error.h index 1dc8e2487..04d126d56 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -147,6 +147,9 @@ public: VARHIDDEN, // Hiding variable WAITCONST, // Wait condition is constant WIDTH, // Width mismatch + WIDTHTRUNC, // Width mismatch- lhs < rhs + WIDTHEXPAND, // Width mismatch- lhs > rhs + WIDTHXZEXPAND, // Width mismatch- lhs > rhs xz filled WIDTHCONCAT, // Unsized numbers/parameters in concatenations ZERODLY, // #0 delay _ENUM_MAX @@ -192,7 +195,7 @@ public: "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", "UNPACKED", "UNSIGNED", "UNUSEDGENVAR", "UNUSEDPARAM", "UNUSEDSIGNAL", "USERERROR", "USERFATAL", "USERINFO", "USERWARN", - "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", "ZERODLY", + "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHTRUNC", "WIDTHEXPAND", "WIDTHXZEXPAND", "WIDTHCONCAT", "ZERODLY", " MAX" }; // clang-format on @@ -223,7 +226,8 @@ public: || m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == IMPLICITSTATIC || m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT - || m_e == UNSIGNED || m_e == WIDTH); + || m_e == UNSIGNED || m_e == WIDTH || m_e == WIDTHTRUNC || m_e == WIDTHEXPAND + || m_e == WIDTHXZEXPAND); } // Warnings that are style only bool styleError() const VL_MT_SAFE { @@ -238,6 +242,20 @@ public: bool unusedError() const VL_MT_SAFE { return (m_e == UNUSEDGENVAR || m_e == UNUSEDPARAM || m_e == UNUSEDSIGNAL); } + + bool isUnder(V3ErrorCode other) { + // backwards compatibility inheritance-like warnings + if (m_e == other) { return true; } + if (other == V3ErrorCode::WIDTH) { + return (m_e == WIDTH || m_e == WIDTHEXPAND || m_e == WIDTHTRUNC + || m_e == WIDTHXZEXPAND); + } + if (other == V3ErrorCode::I_UNUSED) { + return (m_e == UNUSEDGENVAR || m_e == UNUSEDPARAM || m_e == UNUSEDSIGNAL); + } + return false; + } + static bool unusedMsg(const char* msgp) { return 0 == VL_STRCASECMP(msgp, "UNUSED"); } }; constexpr bool operator==(const V3ErrorCode& lhs, const V3ErrorCode& rhs) { @@ -307,7 +325,14 @@ public: } static void abortIfWarnings(); static void suppressThisWarning(); // Suppress next %Warn if user has it off - static void pretendError(V3ErrorCode code, bool flag) { s_pretendError[code] = flag; } + static void pretendError(V3ErrorCode code, bool flag) { + if (code == V3ErrorCode::WIDTH) { + s_pretendError[V3ErrorCode::WIDTHTRUNC] = flag; + s_pretendError[V3ErrorCode::WIDTHEXPAND] = flag; + s_pretendError[V3ErrorCode::WIDTHXZEXPAND] = flag; + } + s_pretendError[code] = flag; + } static bool isError(V3ErrorCode code, bool supp); static string lineStr(const char* filename, int lineno); static V3ErrorCode errorCode() VL_MT_SAFE { return s_errorCode; } @@ -350,6 +375,7 @@ inline void v3errorEndFatal(std::ostringstream& sstr) { // evaluation order as otherwise we couldn't ensure v3errorPrep is called first. #define v3warnCode(code, msg) \ v3errorEnd((V3Error::v3errorPrep(code), (V3Error::v3errorStr() << msg), V3Error::v3errorStr())) + #define v3warnCodeFatal(code, msg) \ v3errorEndFatal( \ (V3Error::v3errorPrep(code), (V3Error::v3errorStr() << msg), V3Error::v3errorStr())) diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 2da4cc73d..e462e2065 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -261,6 +261,11 @@ public: // Turn on/off warning messages on this line. void warnOn(V3ErrorCode code, bool flag) { + if (code == V3ErrorCode::WIDTH) { + warnOn(V3ErrorCode::WIDTHTRUNC, flag); + warnOn(V3ErrorCode::WIDTHEXPAND, flag); + warnOn(V3ErrorCode::WIDTHXZEXPAND, flag); + } m_msgEnIdx = singleton().msgEnSetBit(m_msgEnIdx, code, flag); } void warnOff(V3ErrorCode code, bool flag) { warnOn(code, !flag); } diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 30d58e482..b59dfb899 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -703,7 +703,8 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const { return str; } // case b/d/x/o case 'c': { - if (width() > 8) fl->v3warn(WIDTH, "$display-like format of %c format of > 8 bit value"); + if (width() > 8) + fl->v3warn(WIDTHTRUNC, "$display-like format of %c format of > 8 bit value"); const unsigned int v = bitsValue(0, 8); char strc[2]; strc[0] = v & 0xff; @@ -2243,7 +2244,8 @@ void V3Number::opCleanThis(bool warnOnTruncation) { const uint32_t newValueXMsb = v.m_valueX & hiWordMask(); if (warnOnTruncation && (newValueMsb != v.m_value || newValueXMsb != v.m_valueX)) { // Displaying in decimal avoids hiWordMask truncation - v3warn(WIDTH, "Value too large for " << width() << " bit number: " << displayed("%d")); + v3warn(WIDTHTRUNC, + "Value too large for " << width() << " bit number: " << displayed("%d")); } m_data.num()[words() - 1] = {newValueMsb, newValueXMsb}; } diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 8ea9d7aab..21c452eac 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1564,6 +1564,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char }); DECL_OPTION("-Wno-style", CbCall, []() { FileLine::globalWarnStyleOff(true); }); DECL_OPTION("-Wno-UNUSED", CbCall, []() { FileLine::globalWarnUnusedOff(true); }); + DECL_OPTION("-Wno-WIDTH", CbCall, []() { FileLine::globalWarnOff(V3ErrorCode::WIDTH, true); }); DECL_OPTION("-Wwarn-", CbPartialMatch, [this, fl, &parser](const char* optp) { const V3ErrorCode code{optp}; if (code == V3ErrorCode::EC_ERROR) { @@ -1585,6 +1586,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char V3Error::pretendError(V3ErrorCode::UNUSEDSIGNAL, false); V3Error::pretendError(V3ErrorCode::UNUSEDPARAM, false); }); + DECL_OPTION("-Wwarn-WIDTH", CbCall, []() { + FileLine::globalWarnOff(V3ErrorCode::WIDTH, false); + V3Error::pretendError(V3ErrorCode::WIDTH, false); + }); DECL_OPTION("-waiver-output", Set, &m_waiverOutput); DECL_OPTION("-x-assign", CbVal, [this, fl](const char* valp) { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index e901ae869..272e15471 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -118,6 +118,12 @@ std::ostream& operator<<(std::ostream& str, const Castable& rhs) { return str << s_det[rhs]; } +#define v3widthWarn(lhs, rhs, msg) \ + v3errorEnd((V3Error::v3errorPrep((lhs) < (rhs) ? V3ErrorCode::WIDTHTRUNC \ + : (lhs) > (rhs) ? V3ErrorCode::WIDTHEXPAND \ + : V3ErrorCode::WIDTH), \ + (V3Error::v3errorStr() << msg), V3Error::v3errorStr())) + //###################################################################### // Width state, as a visitor of each AstNode @@ -910,15 +916,16 @@ private: userIterateAndNext(nodep->lsbp(), WidthVP{SELF, FINAL}.p()); if (widthBad(nodep->lsbp(), selwidthDTypep) && nodep->lsbp()->width() != 32) { if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) { - nodep->v3warn(WIDTH, - "Bit extraction of var[" - << (frommsb / elw) << ":" << (fromlsb / elw) << "] requires " - << (selwidth / elw) << " bit index, not " - << (nodep->lsbp()->width() / elw) - << (nodep->lsbp()->width() != nodep->lsbp()->widthMin() - ? " or " + cvtToStr(nodep->lsbp()->widthMin() / elw) - : "") - << " bits."); + nodep->v3widthWarn( + (selwidth / elw), (nodep->lsbp()->width() / elw), + "Bit extraction of var[" + << (frommsb / elw) << ":" << (fromlsb / elw) << "] requires " + << (selwidth / elw) << " bit index, not " + << (nodep->lsbp()->width() / elw) + << (nodep->lsbp()->width() != nodep->lsbp()->widthMin() + ? " or " + cvtToStr(nodep->lsbp()->widthMin() / elw) + : "") + << " bits."); UINFO(1, " Related node: " << nodep << endl); } } @@ -988,13 +995,14 @@ private: AstNodeDType* const selwidthDTypep = nodep->findLogicDType(selwidth, selwidth, nodep->bitp()->dtypep()->numeric()); if (widthBad(nodep->bitp(), selwidthDTypep) && nodep->bitp()->width() != 32) { - nodep->v3warn(WIDTH, "Bit extraction of array[" - << frommsb << ":" << fromlsb << "] requires " << selwidth - << " bit index, not " << nodep->bitp()->width() - << (nodep->bitp()->width() != nodep->bitp()->widthMin() - ? " or " + cvtToStr(nodep->bitp()->widthMin()) - : "") - << " bits."); + nodep->v3widthWarn(selwidth, nodep->bitp()->width(), + "Bit extraction of array[" + << frommsb << ":" << fromlsb << "] requires " << selwidth + << " bit index, not " << nodep->bitp()->width() + << (nodep->bitp()->width() != nodep->bitp()->widthMin() + ? " or " + cvtToStr(nodep->bitp()->widthMin()) + : "") + << " bits."); if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) { UINFO(1, " Related node: " << nodep << endl); UINFO(1, " Related dtype: " << nodep->dtypep() << endl); @@ -6077,8 +6085,9 @@ private: else if (!constp->num().sized() // Make it the proper size. Careful of proper extension of 0's/1's && expWidth > 32 && constp->num().isMsbXZ()) { - constp->v3warn(WIDTH, "Unsized constant being X/Z extended to " - << expWidth << " bits: " << constp->prettyName()); + constp->v3warn(WIDTHXZEXPAND, "Unsized constant being X/Z extended to " + << expWidth + << " bits: " << constp->prettyName()); V3Number num(constp, expWidth); num.opExtendXZ(constp->num(), constp->width()); AstNodeExpr* const newp = new AstConst{constp->fileline(), num}; @@ -6266,15 +6275,16 @@ private: if (bad) { { // if (warnOn), but not needed here if (debug() > 4) nodep->backp()->dumpTree("- back: "); - nodep->v3warn(WIDTH, "Logical operator " - << nodep->prettyTypeName() << " expects 1 bit on the " - << side << ", but " << side << "'s " - << underp->prettyTypeName() << " generates " - << underp->width() - << (underp->width() != underp->widthMin() - ? " or " + cvtToStr(underp->widthMin()) - : "") - << " bits."); + nodep->v3widthWarn(1, underp->width(), + "Logical operator " + << nodep->prettyTypeName() << " expects 1 bit on the " + << side << ", but " << side << "'s " + << underp->prettyTypeName() << " generates " + << underp->width() + << (underp->width() != underp->widthMin() + ? " or " + cvtToStr(underp->widthMin()) + : "") + << " bits."); } VL_DO_DANGLING(fixWidthReduce(VN_AS(underp, NodeExpr)), underp); // Changed } @@ -6448,16 +6458,18 @@ private: } if (bad && warnOn) { if (debug() > 4) nodep->backp()->dumpTree("- back: "); - nodep->v3warn( - WIDTH, ucfirst(nodep->prettyOperatorName()) - << " expects " << expWidth - << (expWidth != expWidthMin ? " or " + cvtToStr(expWidthMin) : "") - << " bits on the " << side << ", but " << side << "'s " - << underp->prettyTypeName() << " generates " << underp->width() - << (underp->width() != underp->widthMin() - ? " or " + cvtToStr(underp->widthMin()) - : "") - << " bits."); + + nodep->v3widthWarn( + expWidth, underp->width(), + ucfirst(nodep->prettyOperatorName()) + << " expects " << expWidth + << (expWidth != expWidthMin ? " or " + cvtToStr(expWidthMin) : "") + << " bits on the " << side << ", but " << side << "'s " + << underp->prettyTypeName() << " generates " << underp->width() + << (underp->width() != underp->widthMin() + ? " or " + cvtToStr(underp->widthMin()) + : "") + << " bits."); } if (bad || underp->width() != expWidth) { // If we're in an NodeAssign, don't truncate the RHS if the LHS is diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index 3ce83ac48..c1b3a1b46 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -2,10 +2,10 @@ : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ -%Warning-WIDTH: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. + : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_class_member_bad.out b/test_regress/t/t_class_member_bad.out index 6488c1673..49570f53f 100644 --- a/test_regress/t/t_class_member_bad.out +++ b/test_regress/t/t_class_member_bad.out @@ -3,10 +3,10 @@ : ... Suggested alternative: 'memb2' 18 | c.memb3 = 3; | ^~~~~ -%Warning-WIDTH: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits. + : ... In instance t 18 | c.memb3 = 3; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index 7aace9782..65358eb59 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTH: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - : ... In instance t +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + : ... In instance t 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz - : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHXZEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHXZEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + : ... In instance t 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; | ^~~ -%Warning-WIDTH: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz - : ... In instance t +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + : ... In instance t 15 | if (68'h?_????????_???????? !== 'd?) $stop; | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_display_cwide_bad.out b/test_regress/t/t_display_cwide_bad.out index f054ce1b7..604986459 100644 --- a/test_regress/t/t_display_cwide_bad.out +++ b/test_regress/t/t_display_cwide_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value +%Warning-WIDTHTRUNC: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value 10 | $display("%c", 32'h1234); | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_dpi_unpack_bad.out b/test_regress/t/t_dpi_unpack_bad.out index 0c7aa4fec..aaaeef547 100644 --- a/test_regress/t/t_dpi_unpack_bad.out +++ b/test_regress/t/t_dpi_unpack_bad.out @@ -3,11 +3,11 @@ 21 | import_func0(sig0); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-WIDTH: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. + : ... In instance t 21 | import_func0(sig0); | ^~~~~~~~~~~~ - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:23:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2]') : ... In instance t 23 | import_func1(sig1); @@ -24,8 +24,8 @@ : ... In instance t 29 | import_func0(sig0[1]); | ^ -%Warning-WIDTH: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits. + : ... In instance t 29 | import_func0(sig0[1]); | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dynarray_bad.out b/test_regress/t/t_dynarray_bad.out index af5fe4a48..a579f8fc8 100644 --- a/test_regress/t/t_dynarray_bad.out +++ b/test_regress/t/t_dynarray_bad.out @@ -1,9 +1,9 @@ -%Warning-WIDTH: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. + : ... In instance t 15 | a = new [s]; | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" 15 | a = new [s]; | ^ diff --git a/test_regress/t/t_flag_context_bad.out b/test_regress/t/t_flag_context_bad.out index 13052d8dd..5cd7f81be 100644 --- a/test_regress/t/t_flag_context_bad.out +++ b/test_regress/t/t_flag_context_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. - : ... In instance t - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. + : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' : ... In instance t %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 844fdafb0..5e0131123 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -1,7 +1,7 @@ -%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index 169d7bcc5..5e0131123 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -1,6 +1,7 @@ -%Error-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For error description see https://verilator.org/warn/WIDTH?v=latest + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index 6ce45b931..8489b1824 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index 03b1ee7dd..af48783fa 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -1,11 +1,11 @@ -%Warning-WIDTH: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. + : ... In instance t 13 | out = MUX (in); | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. - : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. + : ... In instance t 13 | out = MUX (in); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index 5a2a10068..6bf85b1c5 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -1,19 +1,19 @@ -%Warning-WIDTH: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. + : ... In instance t 23 | .outy_w92 (outc_w30), | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. - : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. + : ... In instance t 24 | .outz_w22 (outd_w73), | ^~~~~~~~ -%Warning-WIDTH: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. + : ... In instance t 27 | .inw_w31 (ina_w1), | ^~~~~~~ -%Warning-WIDTH: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. + : ... In instance t 28 | .inx_w11 (inb_w61) | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_literal_bad.out b/test_regress/t/t_lint_literal_bad.out index 5cab1d60b..81f3808be 100644 --- a/test_regress/t/t_lint_literal_bad.out +++ b/test_regress/t/t_lint_literal_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 +%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 35067222b..de1fa2a99 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. - : ... In instance t.sub3 +%Warning-WIDTHTRUNC: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. + : ... In instance t.sub3 18 | wire [0:0] b = a; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_restore_bad.out b/test_regress/t/t_lint_restore_bad.out index a38fcff3e..3f219f8e6 100644 --- a/test_regress/t/t_lint_restore_bad.out +++ b/test_regress/t/t_lint_restore_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTH: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + : ... In instance t 19 | initial five = 64'h1; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index d1faa06e6..dc841f05d 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -1,47 +1,47 @@ -%Warning-WIDTH: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. + : ... In instance t 17 | localparam [3:0] XS = 'hx; | ^~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. - : ... In instance t.p4 + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. + : ... In instance t.p4 47 | wire [4:0] out = in; | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. + : ... In instance t 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; | ^~ -%Warning-WIDTH: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. + : ... In instance t 27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. + : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. + : ... In instance t 37 | initial for (a = 0; a > THREE; ++a) $display(a); | ^ -%Warning-WIDTH: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. + : ... In instance t 38 | initial for (a = 0; a >= THREE; ++a) $display(a); | ^~ -%Warning-WIDTH: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits. + : ... In instance t 40 | initial if (THREE) $stop; | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_docs_bad.out b/test_regress/t/t_lint_width_docs_bad.out deleted file mode 100644 index 0ecd7edd9..000000000 --- a/test_regress/t/t_lint_width_docs_bad.out +++ /dev/null @@ -1,7 +0,0 @@ -%Warning-WIDTH: t/t_lint_width_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits. - : ... In instance t - 10 | wire int rd_value = array[rd_addr]; - | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Error: Exiting due to diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index e94e66164..4e672b104 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -1,23 +1,23 @@ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. + : ... In instance t 25 | rg = g; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. - : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. + : ... In instance t 26 | rp = P; | ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. + : ... In instance t 27 | rw = w; | ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + : ... In instance t 28 | rc = 64'h1; | ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. + : ... In instance t 33 | ri = i; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.out b/test_regress/t/t_lint_widthexpand_docs_bad.out new file mode 100644 index 000000000..241fa51ce --- /dev/null +++ b/test_regress/t/t_lint_widthexpand_docs_bad.out @@ -0,0 +1,7 @@ +%Warning-WIDTHEXPAND: t/t_lint_widthexpand_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits. + : ... In instance t + 10 | wire int rd_value = array[rd_addr]; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_width_docs_bad.pl b/test_regress/t/t_lint_widthexpand_docs_bad.pl similarity index 84% rename from test_regress/t/t_lint_width_docs_bad.pl rename to test_regress/t/t_lint_widthexpand_docs_bad.pl index 1afe476b9..a8b6a6651 100755 --- a/test_regress/t/t_lint_width_docs_bad.pl +++ b/test_regress/t/t_lint_widthexpand_docs_bad.pl @@ -18,18 +18,18 @@ lint( extract( in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTH_1_faulty.rst", + out => "../docs/gen/ex_WIDTHEXPAND_1_faulty.rst", lines => "8-10"); extract( in => $Self->{golden_filename}, - out => "../docs/gen/ex_WIDTH_1_msg.rst", + out => "../docs/gen/ex_WIDTHEXPAND_1_msg.rst", lineno_adjust => -7, regexp => qr/Warning-WIDTH/); extract( in => $Self->{top_filename}, - out => "../docs/gen/ex_WIDTH_1_fixed.rst", + out => "../docs/gen/ex_WIDTHEXPAND_1_fixed.rst", lines => "18"); ok(1); diff --git a/test_regress/t/t_lint_width_docs_bad.v b/test_regress/t/t_lint_widthexpand_docs_bad.v similarity index 100% rename from test_regress/t/t_lint_width_docs_bad.v rename to test_regress/t/t_lint_widthexpand_docs_bad.v diff --git a/test_regress/t/t_math_repl_bad.out b/test_regress/t/t_math_repl_bad.out index 49249a807..18193afbe 100644 --- a/test_regress/t/t_math_repl_bad.out +++ b/test_regress/t/t_math_repl_bad.out @@ -2,12 +2,12 @@ : ... In instance t 12 | o = {0 {1'b1}}; | ^ -%Warning-WIDTH: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. + : ... In instance t 12 | o = {0 {1'b1}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_math_repl_bad.v:13:12: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant. : ... In instance t 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out index 66b235cac..ff5b9a48f 100644 --- a/test_regress/t/t_param_noval_bad.out +++ b/test_regress/t/t_param_noval_bad.out @@ -2,12 +2,12 @@ : ... In instance t 7 | module t #(parameter P); | ^ -%Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. + : ... In instance t 10 | for (j=0; P; j++) | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... In instance t 10 | for (j=0; P; j++) diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out index 3fed6e9b7..3905343e9 100644 --- a/test_regress/t/t_param_width_loc_bad.out +++ b/test_regress/t/t_param_width_loc_bad.out @@ -1,7 +1,7 @@ -%Warning-WIDTH: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. - : ... In instance t.test_i +%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. + : ... In instance t.test_i 25 | parameter logic param = 1'b0 | ^~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range4.out b/test_regress/t/t_select_bad_range4.out index edbedb1b0..302b44d6e 100644 --- a/test_regress/t/t_select_bad_range4.out +++ b/test_regress/t/t_select_bad_range4.out @@ -11,11 +11,11 @@ 20 | sel2 = mi[44 +: -1]; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-WIDTH: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits. + : ... In instance t 20 | sel2 = mi[44 +: -1]; | ^ - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000 : ... In instance t 21 | sel2 = mi[44 +: 1<<29]; @@ -28,8 +28,8 @@ : ... In instance t 21 | sel2 = mi[44 +: 1<<29]; | ^ -%Warning-WIDTH: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits. + : ... In instance t 21 | sel2 = mi[44 +: 1<<29]; | ^ %Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst' @@ -40,16 +40,16 @@ : ... In instance t 22 | sel2 = mi[44 +: nonconst]; | ^~~~~~~~ -%Warning-WIDTH: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + : ... In instance t 22 | sel2 = mi[44 +: nonconst]; | ^ -%Warning-WIDTH: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits. + : ... In instance t 23 | sel2 = mi[nonconst]; | ^~~~~~~~ -%Warning-WIDTH: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + : ... In instance t 23 | sel2 = mi[nonconst]; | ^ %Error: t/t_select_bad_range4.v:24:17: Expecting expression to be constant, but variable isn't const: 'nonconst' @@ -68,8 +68,8 @@ : ... In instance t 24 | sel2 = mi[nonconst : nonconst]; | ^~~~~~~~ -%Warning-WIDTH: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. + : ... In instance t 24 | sel2 = mi[nonconst : nonconst]; | ^ %Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 20000001 bits from only 6 bit number @@ -80,8 +80,8 @@ : ... In instance t 25 | sel2 = mi[1<<29 : 0]; | ^ -%Warning-WIDTH: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits. + : ... In instance t 25 | sel2 = mi[1<<29 : 0]; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range5.out b/test_regress/t/t_select_bad_range5.out index b97758309..0c84ef079 100644 --- a/test_regress/t/t_select_bad_range5.out +++ b/test_regress/t/t_select_bad_range5.out @@ -12,8 +12,8 @@ : ... In instance t 16 | assign mi = unk[3:2]; | ^ -%Warning-WIDTH: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. + : ... In instance t 16 | assign mi = unk[3:2]; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index 6249c2943..0b8fbf11a 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -19,8 +19,8 @@ : ... In instance t.i_sub3 90 | assign outwires[12] = inwires[13]; | ^ -%Warning-WIDTH: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. + : ... In instance t 41 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); | ^ %Error: t/t_split_var_1_bad.v:79:16: Illegal assignment of constant to unpacked array diff --git a/test_regress/t/t_stream_bad.out b/test_regress/t/t_stream_bad.out index d374c004f..970a91901 100644 --- a/test_regress/t/t_stream_bad.out +++ b/test_regress/t/t_stream_bad.out @@ -6,10 +6,10 @@ : ... In instance t 12 | initial packed_data_32 = {<<$random{byte_in}}; | ^~ -%Warning-WIDTH: t/t_stream_bad.v:12:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_bad.v:12:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. + : ... In instance t 12 | initial packed_data_32 = {<<$random{byte_in}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_stream_integer_type.out b/test_regress/t/t_stream_integer_type.out index 96728e3ee..ab803e9a1 100644 --- a/test_regress/t/t_stream_integer_type.out +++ b/test_regress/t/t_stream_integer_type.out @@ -1,147 +1,147 @@ -%Warning-WIDTH: t/t_stream_integer_type.v:118:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:118:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. + : ... In instance t 118 | packed_data_32 = {<<8{byte_in}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=latest - ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. - : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. + : ... In instance t 119 | packed_data_64 = {<<16{shortint_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:120:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:120:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. + : ... In instance t 120 | packed_data_128 = {<<32{int_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:121:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:121:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. + : ... In instance t 121 | packed_data_128_i = {<<32{integer_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:122:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:122:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits. + : ... In instance t 122 | packed_data_256 = {<<64{longint_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:123:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:123:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits. + : ... In instance t 123 | packed_time_256 = {<<64{time_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:124:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:124:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. + : ... In instance t 124 | v_packed_data_32 = {<<8{bit_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:125:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:125:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. + : ... In instance t 125 | v_packed_data_64 = {<<16{logic_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:126:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:126:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits. + : ... In instance t 126 | v_packed_data_128 = {<<32{reg_in}}; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:128:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:128:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits. + : ... In instance t 128 | {<<8{byte_out}} = packed_data_32; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:129:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:129:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits. + : ... In instance t 129 | {<<16{shortint_out}} = packed_data_64; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:130:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:130:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits. + : ... In instance t 130 | {<<32{int_out}} = packed_data_128; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:131:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:131:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits. + : ... In instance t 131 | {<<32{integer_out}} = packed_data_128_i; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:132:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:132:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits. + : ... In instance t 132 | {<<64{longint_out}} = packed_data_256; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:133:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:133:31: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits. + : ... In instance t 133 | {<<64{time_out}} = packed_time_256; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:134:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:134:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits. + : ... In instance t 134 | {<<8{bit_out}} = v_packed_data_32; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:135:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:135:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits. + : ... In instance t 135 | {<<16{logic_out}} = v_packed_data_64; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:136:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits. - : ... In instance t +%Warning-WIDTHTRUNC: t/t_stream_integer_type.v:136:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits. + : ... In instance t 136 | {<<32{reg_out}} = v_packed_data_128; | ^ -%Warning-WIDTH: t/t_stream_integer_type.v:150:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. - : ... In instance t +%Warning-WIDTHEXPAND: t/t_stream_integer_type.v:150:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits. + : ... In instance t 150 | packed_data_32 = {<