Fix tracing with awaits at end of block (#4075) (#4076)

Given an await at the end of a block, e.g. at the end of a loop body, a trace
activity setter was not inserted, as there were no following statements. This
patch makes the activity update unconditional.
This commit is contained in:
Krzysztof Bieganski 2023-03-31 19:51:31 +02:00 committed by GitHub
parent 0b96789e65
commit d012563ab1
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 84 additions and 54 deletions

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@ -437,7 +437,7 @@ private:
funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) { funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
AstNode* stmtp = awaitp->backp(); AstNode* stmtp = awaitp->backp();
while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp(); while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
if (stmtp->nextp()) stmtp->addNextHere(setterp->cloneTree(false)); stmtp->addNextHere(setterp->cloneTree(false));
}); });
} }
funcp->addStmtsp(setterp); funcp->addStmtsp(setterp);

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@ -1,5 +1,4 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$date Tue Nov 22 16:48:14 2022 $end
$timescale 1ps $end $timescale 1ps $end
$scope module TOP $end $scope module TOP $end
@ -7,11 +6,11 @@ $timescale 1ps $end
$var wire 32 + CLK_HALF_PERIOD [31:0] $end $var wire 32 + CLK_HALF_PERIOD [31:0] $end
$var wire 32 * CLK_PERIOD [31:0] $end $var wire 32 * CLK_PERIOD [31:0] $end
$var wire 1 $ a $end $var wire 1 $ a $end
$var wire 1 % b $end $var wire 1 ) b $end
$var wire 1 & c $end $var wire 1 % c $end
$var wire 1 ) clk $end $var wire 1 ( clk $end
$var wire 1 ' d $end $var wire 1 & d $end
$var event 1 ( ev $end $var event 1 ' ev $end
$var wire 1 # rst $end $var wire 1 # rst $end
$upscope $end $upscope $end
$upscope $end $upscope $end
@ -21,60 +20,77 @@ $enddefinitions $end
#0 #0
1# 1#
0$ 0$
0% 1%
0& 0&
0' 1'
0) 0(
1)
b00000000000000000000000000001010 * b00000000000000000000000000001010 *
b00000000000000000000000000000101 + b00000000000000000000000000000101 +
#5 #5
1) 1(
#10 #10
0# 0%
1% 1'
1( 0(
0)
#15 #15
1)
#20
1( 1(
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1( 1(
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1)

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@ -29,18 +29,16 @@ module t;
clk = 0; clk = 0;
a = 0; a = 0;
c = 0; c = 0;
b = 0; b = ~b;
d = 0; d = 0;
#CLK_PERIOD; fork #(10 * CLK_PERIOD) b = 0; join_none
rst = 0;
b = 1;
-> ev ;
#CLK_PERIOD;
-> ev ;
#(9 * CLK_PERIOD); while (b) begin
-> ev ; c = ~c;
-> ev ;
#CLK_PERIOD;
end
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

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@ -1,5 +1,5 @@
$date $date
Tue Nov 22 18:14:18 2022 Fri Mar 31 18:34:51 2023
$end $end
$version $version
@ -26,8 +26,8 @@ $enddefinitions $end
$dumpvars $dumpvars
1) 1)
0( 0(
0' 1'
0& 1&
0% 0%
0$ 0$
1# 1#
@ -38,50 +38,66 @@ $end
1$ 1$
#10 #10
0$ 0$
0# 0'
1&
1) 1)
#15 #15
1$ 1$
#20 #20
0$ 0$
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#105 #105
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#110 #110
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1#