From d012563ab13911cda37ccb670fab43a362223c8e Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Fri, 31 Mar 2023 19:51:31 +0200
Subject: [PATCH] Fix tracing with awaits at end of block (#4075) (#4076)

Given an await at the end of a block, e.g. at the end of a loop body, a trace
activity setter was not inserted, as there were no following statements. This
patch makes the activity update unconditional.
---
 src/V3Trace.cpp                       |  2 +-
 test_regress/t/t_timing_trace.out     | 90 ++++++++++++++++-----------
 test_regress/t/t_timing_trace.v       | 16 +++--
 test_regress/t/t_timing_trace_fst.out | 30 ++++++---
 4 files changed, 84 insertions(+), 54 deletions(-)

diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index d7669f62d..44a12ba59 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -437,7 +437,7 @@ private:
                 funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
                     AstNode* stmtp = awaitp->backp();
                     while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
-                    if (stmtp->nextp()) stmtp->addNextHere(setterp->cloneTree(false));
+                    stmtp->addNextHere(setterp->cloneTree(false));
                 });
             }
             funcp->addStmtsp(setterp);
diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out
index f1a84fcb5..9328aceca 100644
--- a/test_regress/t/t_timing_trace.out
+++ b/test_regress/t/t_timing_trace.out
@@ -1,5 +1,4 @@
 $version Generated by VerilatedVcd $end
-$date Tue Nov 22 16:48:14 2022 $end
 $timescale 1ps $end
 
  $scope module TOP $end
@@ -7,11 +6,11 @@ $timescale 1ps $end
    $var wire 32 + CLK_HALF_PERIOD [31:0] $end
    $var wire 32 * CLK_PERIOD [31:0] $end
    $var wire  1 $ a $end
-   $var wire  1 % b $end
-   $var wire  1 & c $end
-   $var wire  1 ) clk $end
-   $var wire  1 ' d $end
-   $var event  1 ( ev $end
+   $var wire  1 ) b $end
+   $var wire  1 % c $end
+   $var wire  1 ( clk $end
+   $var wire  1 & d $end
+   $var event  1 ' ev $end
    $var wire  1 # rst $end
   $upscope $end
  $upscope $end
@@ -21,60 +20,77 @@ $enddefinitions $end
 #0
 1#
 0$
-0%
+1%
 0&
-0'
-0)
+1'
+0(
+1)
 b00000000000000000000000000001010 *
 b00000000000000000000000000000101 +
 #5
-1)
+1(
 #10
-0#
-1%
-1(
-0)
+0%
+1'
+0(
 #15
-1)
-#20
 1(
-0)
+#20
+1%
+1'
+0(
 #25
-1)
+1(
 #30
-0)
+0%
+1'
+0(
 #35
-1)
+1(
 #40
-0)
+1%
+1'
+0(
 #45
-1)
+1(
 #50
-0)
+0%
+1'
+0(
 #55
-1)
+1(
 #60
-0)
+1%
+1'
+0(
 #65
-1)
+1(
 #70
-0)
+0%
+1'
+0(
 #75
-1)
+1(
 #80
-0)
+1%
+1'
+0(
 #85
-1)
+1(
 #90
-0)
+0%
+1'
+0(
 #95
-1)
+1(
 #100
+1%
+1'
+0(
 0)
 #105
-1)
-#110
-1#
-0%
 1(
-0)
+#110
+1'
+0(
+1)
diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v
index 9893856cc..fa1471eb5 100644
--- a/test_regress/t/t_timing_trace.v
+++ b/test_regress/t/t_timing_trace.v
@@ -29,18 +29,16 @@ module t;
         clk = 0;
         a = 0;
         c = 0;
-        b = 0;
+        b = ~b;
         d = 0;
 
-        #CLK_PERIOD;
-        rst = 0;
-        b = 1;
-        -> ev ;
-        #CLK_PERIOD;
-        -> ev ;
+        fork #(10 * CLK_PERIOD) b = 0; join_none
 
-        #(9 * CLK_PERIOD);
-        -> ev ;
+        while (b) begin
+            c = ~c;
+            -> ev ;
+            #CLK_PERIOD;
+        end
 
         $write("*-* All Finished *-*\n");
         $finish;
diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_timing_trace_fst.out
index a0170939c..44e15ea4b 100644
--- a/test_regress/t/t_timing_trace_fst.out
+++ b/test_regress/t/t_timing_trace_fst.out
@@ -1,5 +1,5 @@
 $date
-	Tue Nov 22 18:14:18 2022
+	Fri Mar 31 18:34:51 2023
 
 $end
 $version
@@ -26,8 +26,8 @@ $enddefinitions $end
 $dumpvars
 1)
 0(
-0'
-0&
+1'
+1&
 0%
 0$
 1#
@@ -38,50 +38,66 @@ $end
 1$
 #10
 0$
-0#
-1&
+0'
 1)
 #15
 1$
 #20
 0$
 1)
+1'
 #25
 1$
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+0'
+1)
 #35
 1$
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+1)
+1'
 #45
 1$
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+0'
+1)
 #55
 1$
 #60
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+1)
+1'
 #65
 1$
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+0'
+1)
 #75
 1$
 #80
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+1)
+1'
 #85
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+0'
+1)
 #95
 1$
 #100
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+1)
+1'
+0&
 #105
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 #110
 0$
+1&
 1)
-0&
-1#