forked from github/verilator
Tests: Unsupported test for bug1627.
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
parent
dcbdac1b81
commit
cff5485821
17
test_regress/t/t_unpacked_concat_bad.out
Normal file
17
test_regress/t/t_unpacked_concat_bad.out
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
%Warning-WIDTHCONCAT: t/t_typedef_logic_in_concat_bad.v:12: Unsized numbers/parameters not allowed in replications.
|
||||||
|
: ... In instance t
|
||||||
|
typedef logic [15:0] count_t;
|
||||||
|
^~~~~
|
||||||
|
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
|
||||||
|
%Error: Exiting due to 1 warning(s)
|
||||||
|
|
||||||
|
# This warning message is pretty misleading. Instead of pointing out to the call to $bits() without a cast, it points to the type declaration of the argument to bits. It would be more useful if it looked like this:
|
||||||
|
|
||||||
|
%Warning-WIDTHCONCAT: t/t_typedef_logic_in_concat_bad.v:15: Unsized numbers/parameters not allowed in replications.
|
||||||
|
: ... In instance t
|
||||||
|
localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}};
|
||||||
|
^~~~~
|
||||||
|
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
|
||||||
|
%Error: Exiting due to 1 warning(s)
|
||||||
|
|
||||||
|
|
20
test_regress/t/t_unpacked_concat_bad.pl
Executable file
20
test_regress/t/t_unpacked_concat_bad.pl
Executable file
@ -0,0 +1,20 @@
|
|||||||
|
#!/usr/bin/perl
|
||||||
|
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||||
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||||
|
#
|
||||||
|
# Copyright 2019 by Wilson Snyder. This program is free software; you can
|
||||||
|
# redistribute it and/or modify it under the terms of either the GNU
|
||||||
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||||
|
# Version 2.0.
|
||||||
|
|
||||||
|
scenarios(linter => 1);
|
||||||
|
|
||||||
|
$Self->{vlt_all} and unsupported("Verilator unsupported, bug1627");
|
||||||
|
|
||||||
|
lint(
|
||||||
|
fails => 1,
|
||||||
|
expect_filename => $Self->{golden_filename},
|
||||||
|
);
|
||||||
|
|
||||||
|
ok(1);
|
||||||
|
1;
|
24
test_regress/t/t_unpacked_concat_bad.v
Normal file
24
test_regress/t/t_unpacked_concat_bad.v
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
// DESCRIPTION: Verilator: Verilog Test module
|
||||||
|
//
|
||||||
|
// This file ONLY is placed into the Public Domain, for any use,
|
||||||
|
// without warranty, 2019 by Driss Hafdi
|
||||||
|
|
||||||
|
module t (/*AUTOARG*/
|
||||||
|
// Inputs
|
||||||
|
clk
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
typedef logic [15:0] count_t;
|
||||||
|
typedef bit [31:0] bit_int_t;
|
||||||
|
|
||||||
|
localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}};
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$write("%d\n", count_bits[0]);
|
||||||
|
$write("%d\n", count_bits[1]);
|
||||||
|
$write("*-* All Finished *-*\n");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
endmodule
|
Loading…
Reference in New Issue
Block a user