diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out new file mode 100644 index 000000000..5a027afdc --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -0,0 +1,17 @@ +%Warning-WIDTHCONCAT: t/t_typedef_logic_in_concat_bad.v:12: Unsized numbers/parameters not allowed in replications. + : ... In instance t + typedef logic [15:0] count_t; + ^~~~~ + ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. +%Error: Exiting due to 1 warning(s) + +# This warning message is pretty misleading. Instead of pointing out to the call to $bits() without a cast, it points to the type declaration of the argument to bits. It would be more useful if it looked like this: + +%Warning-WIDTHCONCAT: t/t_typedef_logic_in_concat_bad.v:15: Unsized numbers/parameters not allowed in replications. + : ... In instance t + localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + ^~~~~ + ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. +%Error: Exiting due to 1 warning(s) + + diff --git a/test_regress/t/t_unpacked_concat_bad.pl b/test_regress/t/t_unpacked_concat_bad.pl new file mode 100755 index 000000000..3dac40252 --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(linter => 1); + +$Self->{vlt_all} and unsupported("Verilator unsupported, bug1627"); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_unpacked_concat_bad.v b/test_regress/t/t_unpacked_concat_bad.v new file mode 100644 index 000000000..685a5e5ca --- /dev/null +++ b/test_regress/t/t_unpacked_concat_bad.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Driss Hafdi + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + typedef logic [15:0] count_t; + typedef bit [31:0] bit_int_t; + + localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + + initial begin + $write("%d\n", count_bits[0]); + $write("%d\n", count_bits[1]); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule