Fix class unpacked-array compile error (#2774).

Changes

@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Verilated signals now use VlWide and VlPacked in place of C arrays.
 
+****  Fix class unpacked-array compile error (#2774). [Iru Cai]
+
 
 * Verilator 4.200 2021-03-12
 

include/verilated_heavy.h

@@ -827,8 +827,24 @@ public:
 
     T_Value& operator[](size_t index) { return m_array[index]; };
     const T_Value& operator[](size_t index) const { return m_array[index]; };
+
+    // Dumping. Verilog: str = $sformatf("%p", assoc)
+    std::string to_string() const {
+        std::string out = "'{";
+        std::string comma;
+        for (int i = 0; i < T_Depth; ++i) {
+            out += comma + VL_TO_STRING(m_array[i]);
+            comma = ", ";
+        }
+        return out + "} ";
+    }
 };
 
+template <class T_Value, std::size_t T_Depth>
+std::string VL_TO_STRING(const VlUnpacked<T_Value, T_Depth>& obj) {
+    return obj.to_string();
+}
+
 //===================================================================
 // Verilog class reference container
 // There are no multithreaded locks on this; the base variable must

test_regress/t/t_class_format.out

@@ -0,0 +1,2 @@
+''{b:'h1, i:'h2a, carray4:'{'h0, 'h0, 'h0, 'h0} }'
+*-* All Finished *-*

test_regress/t/t_class_format.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_class_format.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`ifdef verilator
+ `define stop $stop
+`else
+ `define stop
+`endif
+`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+
+class Cls;
+   bit b;
+   int i;
+   bit [15:0] carray4 [4];
+endclass
+
+module t (/*AUTOARG*/);
+   initial begin
+      Cls c;
+      c = new;
+      c.b = '1;
+      c.i = 42;
+      $display("'%p'", c);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule