From ce79c4ebf948e4267af87b63a21c3e2a7ad5a4f6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 12:47:19 -0500 Subject: [PATCH] Fix class unpacked-array compile error (#2774). --- Changes | 2 ++ include/verilated_heavy.h | 16 ++++++++++++++++ test_regress/t/t_class_format.out | 2 ++ test_regress/t/t_class_format.pl | 22 ++++++++++++++++++++++ test_regress/t/t_class_format.v | 31 +++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+) create mode 100644 test_regress/t/t_class_format.out create mode 100755 test_regress/t/t_class_format.pl create mode 100644 test_regress/t/t_class_format.v diff --git a/Changes b/Changes index b4f984768..e0740eebf 100644 --- a/Changes +++ b/Changes @@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Verilated signals now use VlWide and VlPacked in place of C arrays. +**** Fix class unpacked-array compile error (#2774). [Iru Cai] + * Verilator 4.200 2021-03-12 diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index a3cb94441..19df8b552 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -827,8 +827,24 @@ public: T_Value& operator[](size_t index) { return m_array[index]; }; const T_Value& operator[](size_t index) const { return m_array[index]; }; + + // Dumping. Verilog: str = $sformatf("%p", assoc) + std::string to_string() const { + std::string out = "'{"; + std::string comma; + for (int i = 0; i < T_Depth; ++i) { + out += comma + VL_TO_STRING(m_array[i]); + comma = ", "; + } + return out + "} "; + } }; +template +std::string VL_TO_STRING(const VlUnpacked& obj) { + return obj.to_string(); +} + //=================================================================== // Verilog class reference container // There are no multithreaded locks on this; the base variable must diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out new file mode 100644 index 000000000..8005604fe --- /dev/null +++ b/test_regress/t/t_class_format.out @@ -0,0 +1,2 @@ +''{b:'h1, i:'h2a, carray4:'{'h0, 'h0, 'h0, 'h0} }' +*-* All Finished *-* diff --git a/test_regress/t/t_class_format.pl b/test_regress/t/t_class_format.pl new file mode 100755 index 000000000..03b63c1a0 --- /dev/null +++ b/test_regress/t/t_class_format.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v new file mode 100644 index 000000000..a280d126b --- /dev/null +++ b/test_regress/t/t_class_format.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`ifdef verilator + `define stop $stop +`else + `define stop +`endif +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +class Cls; + bit b; + int i; + bit [15:0] carray4 [4]; +endclass + +module t (/*AUTOARG*/); + initial begin + Cls c; + c = new; + c.b = '1; + c.i = 42; + $display("'%p'", c); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule