Fix incorrect width after and-or optimization (#3208).

This commit is contained in:
Wilson Snyder 2021-11-23 18:15:21 -05:00
parent b1b92b7dd4
commit c14bbb9421
6 changed files with 62 additions and 2 deletions

View File

@ -25,6 +25,7 @@ Verilator 4.215 devel
* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
* Fix display of signed without format (#3204). [Julie Schwartz]
* Fix display of empty string constant (#3207). [Julie Schwartz]
* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
* Fix %0 format on $value$plusargs.

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@ -1670,6 +1670,7 @@ private:
if (operandsSame(llp, rlp)) {
lp->lhsp(llp);
lp->rhsp(nodep);
lp->dtypeFrom(nodep);
nodep->lhsp(lrp);
nodep->rhsp(rrp);
VL_DO_DANGLING(rp->deleteTree(), rp);
@ -1677,6 +1678,7 @@ private:
} else if (operandsSame(lrp, rrp)) {
lp->lhsp(nodep);
lp->rhsp(rrp);
lp->dtypeFrom(nodep);
nodep->lhsp(llp);
nodep->rhsp(rlp);
VL_DO_DANGLING(rp->deleteTree(), rp);

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@ -283,8 +283,8 @@ class Cpt:
self.print("\t// " + typefunc['comment'] + "\n")
self.print("\tif (" + typefunc['match_if'] + ") {\n")
self.print("\t UINFO(" + str(typefunc['uinfo_level']) +
",cvtToHex(nodep)" + "<<\" " + typefunc['uinfo'] +
"\\n\");\n")
", cvtToHex(nodep)" + " << \" " +
typefunc['uinfo'] + "\\n\");\n")
self.print("\t " + typefunc['exec_func'] + "\n")
self.print("\t return true;\n")
self.print("\t}\n")

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@ -0,0 +1,3 @@
abcd=abcd
ab0d=ab0d
*-* All Finished *-*

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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,32 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc = 0;
always @ (posedge clk) ++cyc;
reg [15 : 0] t2;
always@(posedge clk) begin
if (cyc == 0) begin
t2 <= 16'd0;
end
else if (cyc == 2) begin
t2 <= 16'habcd;
end
else if (cyc == 4) begin
$display("abcd=%x", t2);
$display("ab0d=%x", { t2[15:8], 4'd0, t2[3:0] });
$write("*-* All Finished *-*\n");
$finish(32'd0);
end
end
endmodule