forked from github/verilator
Fix incorrect width after and-or optimization (#3208).
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Changes
@ -25,6 +25,7 @@ Verilator 4.215 devel
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* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
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* Fix display of signed without format (#3204). [Julie Schwartz]
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* Fix display of empty string constant (#3207). [Julie Schwartz]
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* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
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* Fix %0 format on $value$plusargs.
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@ -1670,6 +1670,7 @@ private:
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if (operandsSame(llp, rlp)) {
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lp->lhsp(llp);
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lp->rhsp(nodep);
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lp->dtypeFrom(nodep);
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nodep->lhsp(lrp);
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nodep->rhsp(rrp);
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VL_DO_DANGLING(rp->deleteTree(), rp);
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@ -1677,6 +1678,7 @@ private:
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} else if (operandsSame(lrp, rrp)) {
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lp->lhsp(nodep);
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lp->rhsp(rrp);
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lp->dtypeFrom(nodep);
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nodep->lhsp(llp);
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nodep->rhsp(rlp);
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VL_DO_DANGLING(rp->deleteTree(), rp);
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@ -283,8 +283,8 @@ class Cpt:
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self.print("\t// " + typefunc['comment'] + "\n")
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self.print("\tif (" + typefunc['match_if'] + ") {\n")
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self.print("\t UINFO(" + str(typefunc['uinfo_level']) +
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",cvtToHex(nodep)" + "<<\" " + typefunc['uinfo'] +
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"\\n\");\n")
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", cvtToHex(nodep)" + " << \" " +
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typefunc['uinfo'] + "\\n\");\n")
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self.print("\t " + typefunc['exec_func'] + "\n")
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self.print("\t return true;\n")
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self.print("\t}\n")
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3
test_regress/t/t_display_concat.out
Normal file
3
test_regress/t/t_display_concat.out
Normal file
@ -0,0 +1,3 @@
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abcd=abcd
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ab0d=ab0d
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*-* All Finished *-*
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22
test_regress/t/t_display_concat.pl
Executable file
22
test_regress/t/t_display_concat.pl
Executable file
@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2021 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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32
test_regress/t/t_display_concat.v
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32
test_regress/t/t_display_concat.v
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@ -0,0 +1,32 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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always @ (posedge clk) ++cyc;
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reg [15 : 0] t2;
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always@(posedge clk) begin
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if (cyc == 0) begin
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t2 <= 16'd0;
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end
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else if (cyc == 2) begin
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t2 <= 16'habcd;
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end
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else if (cyc == 4) begin
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$display("abcd=%x", t2);
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$display("ab0d=%x", { t2[15:8], 4'd0, t2[3:0] });
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$write("*-* All Finished *-*\n");
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$finish(32'd0);
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end
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end
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endmodule
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