Fix hang on recursive definition error (#3199).

This commit is contained in:
Wilson Snyder 2021-11-23 07:27:41 -05:00
parent a14394dbb5
commit b1b92b7dd4
5 changed files with 54 additions and 2 deletions

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@ -22,6 +22,7 @@ Verilator 4.215 devel
* Fix array method names with parenthesis (#3181) (#3183). [Teng Huang]
* Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA]
* Fix nested generate if genblk naming (#3189). [yanx21]
* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
* Fix display of signed without format (#3204). [Julie Schwartz]
* Fix display of empty string constant (#3207). [Julie Schwartz]
* Fix %0 format on $value$plusargs.

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@ -2952,8 +2952,16 @@ private:
nodep->classOrPackagep(foundp->classOrPackagep());
} else if (AstParamTypeDType* defp
= foundp ? VN_CAST(foundp->nodep(), ParamTypeDType) : nullptr) {
nodep->refDTypep(defp);
nodep->classOrPackagep(foundp->classOrPackagep());
if (defp == nodep->backp()) { // Where backp is typically typedef
nodep->v3error("Reference to '" << m_ds.m_dotText
<< (m_ds.m_dotText == "" ? "" : ".")
<< nodep->prettyName() << "'"
<< " type would form a recursive definition");
nodep->refDTypep(nodep->findVoidDType()); // Try to reduce later errors
} else {
nodep->refDTypep(defp);
nodep->classOrPackagep(foundp->classOrPackagep());
}
} else if (AstClass* defp = foundp ? VN_AS(foundp->nodep(), Class) : nullptr) {
AstNode* paramsp = nodep->paramsp();
if (paramsp) paramsp->unlinkFrBackWithNext();

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@ -0,0 +1,4 @@
%Error: t/t_type_param_circ_bad.v:14:27: Reference to 'SZ' type would form a recursive definition
14 | # (parameter type SZ = SZ)
| ^~
%Error: Exiting due to

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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,20 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package pkg;
parameter [7:0] WIDTH = 8;
typedef logic [WIDTH-1:0] SZ;
endpackage // pkg
module t
import pkg::*;
# (parameter type SZ = SZ)
(input SZ i,
output SZ o);
always_comb o = i;
endmodule