forked from github/verilator
Fix hang on recursive definition error (#3199).
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@ -22,6 +22,7 @@ Verilator 4.215 devel
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* Fix array method names with parenthesis (#3181) (#3183). [Teng Huang]
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* Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA]
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* Fix nested generate if genblk naming (#3189). [yanx21]
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* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
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* Fix display of signed without format (#3204). [Julie Schwartz]
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* Fix display of empty string constant (#3207). [Julie Schwartz]
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* Fix %0 format on $value$plusargs.
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@ -2952,8 +2952,16 @@ private:
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nodep->classOrPackagep(foundp->classOrPackagep());
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} else if (AstParamTypeDType* defp
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= foundp ? VN_CAST(foundp->nodep(), ParamTypeDType) : nullptr) {
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nodep->refDTypep(defp);
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nodep->classOrPackagep(foundp->classOrPackagep());
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if (defp == nodep->backp()) { // Where backp is typically typedef
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nodep->v3error("Reference to '" << m_ds.m_dotText
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<< (m_ds.m_dotText == "" ? "" : ".")
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<< nodep->prettyName() << "'"
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<< " type would form a recursive definition");
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nodep->refDTypep(nodep->findVoidDType()); // Try to reduce later errors
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} else {
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nodep->refDTypep(defp);
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nodep->classOrPackagep(foundp->classOrPackagep());
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}
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} else if (AstClass* defp = foundp ? VN_AS(foundp->nodep(), Class) : nullptr) {
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AstNode* paramsp = nodep->paramsp();
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if (paramsp) paramsp->unlinkFrBackWithNext();
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4
test_regress/t/t_type_param_circ_bad.out
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4
test_regress/t/t_type_param_circ_bad.out
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@ -0,0 +1,4 @@
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%Error: t/t_type_param_circ_bad.v:14:27: Reference to 'SZ' type would form a recursive definition
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14 | # (parameter type SZ = SZ)
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| ^~
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%Error: Exiting due to
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19
test_regress/t/t_type_param_circ_bad.pl
Executable file
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test_regress/t/t_type_param_circ_bad.pl
Executable file
@ -0,0 +1,19 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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lint(
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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20
test_regress/t/t_type_param_circ_bad.v
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20
test_regress/t/t_type_param_circ_bad.v
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@ -0,0 +1,20 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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parameter [7:0] WIDTH = 8;
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typedef logic [WIDTH-1:0] SZ;
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endpackage // pkg
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module t
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import pkg::*;
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# (parameter type SZ = SZ)
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(input SZ i,
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output SZ o);
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always_comb o = i;
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endmodule
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