Fix final duplicate declarations when non-inlined, bug661.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Fix vpi_iterate on memory words, bug655. [Rich Porter]
 
+****  Fix final duplicate declarations when non-inlined, bug661. [Charlie Brej]
+
 ****  Fix interface ports with comma lists, msg1058. [Ed Lander]
 
 ****  Fix clang warnings, bug668.  [Yutetsu Takatsukasa]

src/V3Active.cpp

@@ -291,7 +291,7 @@ private:
 	}
 	ActiveDlyVisitor dlyvisitor (nodep, ActiveDlyVisitor::CT_INITIAL);
 	if (!m_scopeFinalp) {
-	    m_scopeFinalp = new AstCFunc(nodep->fileline(), "_final", m_namer.scopep());
+	    m_scopeFinalp = new AstCFunc(nodep->fileline(), "_final_"+m_namer.scopep()->nameDotless(), m_namer.scopep());
 	    m_scopeFinalp->argTypes(EmitCBaseVisitor::symClassVar());
 	    m_scopeFinalp->addInitsp(new AstCStmt(nodep->fileline(), EmitCBaseVisitor::symTopAssign()+"\n"));
 	    m_scopeFinalp->dontCombine(true);

src/V3Clock.cpp

@@ -346,14 +346,10 @@ private:
 	nodep->iterateChildren(*this);
 	// Link to global function
 	if (nodep->formCallTree()) {
-	    if (nodep->name() == "_final") {
+	    UINFO(4, "    formCallTree "<<nodep<<endl);
-		UINFO(4, "    formCallTree "<<nodep<<endl);
+	    AstCCall* callp = new AstCCall(nodep->fileline(), nodep);
-		AstCCall* callp = new AstCCall(nodep->fileline(), nodep);
+	    callp->argTypes("vlSymsp");
-		callp->argTypes("vlSymsp");
+	    m_finalFuncp->addStmtsp(callp);
-		m_finalFuncp->addStmtsp(callp);
-	    } else {
-		nodep->v3fatalSrc("Unknown CFunc name.  Make code more generic, with a map of func names");
-	    }
 	}
     }
     virtual void visit(AstSenTree* nodep, AstNUser*) {

test_regress/t/t_final.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_final.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Charlie Brej.
+
+module submodule ();
+   // This bug only appears when not inlining
+   // verilator no_inline_module
+   initial begin
+      $write("d");
+   end
+   final begin
+      $write("d");
+   end
+endmodule
+
+module t ();
+   generate
+      for (genvar i = 0; i < 100; i = i + 1) begin : module_set
+	 submodule u_submodule ();
+      end
+   endgenerate
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule