From bebf5b291bf5666e5764ec7b965eb673193e6c9f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 29 Jul 2013 21:47:23 -0400 Subject: [PATCH] Fix final duplicate declarations when non-inlined, bug661. --- Changes | 2 ++ src/V3Active.cpp | 2 +- src/V3Clock.cpp | 12 ++++-------- test_regress/t/t_final.pl | 18 ++++++++++++++++++ test_regress/t/t_final.v | 27 +++++++++++++++++++++++++++ 5 files changed, 52 insertions(+), 9 deletions(-) create mode 100755 test_regress/t/t_final.pl create mode 100644 test_regress/t/t_final.v diff --git a/Changes b/Changes index da42dd133..00872b6b8 100644 --- a/Changes +++ b/Changes @@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks! *** Fix vpi_iterate on memory words, bug655. [Rich Porter] +**** Fix final duplicate declarations when non-inlined, bug661. [Charlie Brej] + **** Fix interface ports with comma lists, msg1058. [Ed Lander] **** Fix clang warnings, bug668. [Yutetsu Takatsukasa] diff --git a/src/V3Active.cpp b/src/V3Active.cpp index dd5150d2b..f221cf468 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -291,7 +291,7 @@ private: } ActiveDlyVisitor dlyvisitor (nodep, ActiveDlyVisitor::CT_INITIAL); if (!m_scopeFinalp) { - m_scopeFinalp = new AstCFunc(nodep->fileline(), "_final", m_namer.scopep()); + m_scopeFinalp = new AstCFunc(nodep->fileline(), "_final_"+m_namer.scopep()->nameDotless(), m_namer.scopep()); m_scopeFinalp->argTypes(EmitCBaseVisitor::symClassVar()); m_scopeFinalp->addInitsp(new AstCStmt(nodep->fileline(), EmitCBaseVisitor::symTopAssign()+"\n")); m_scopeFinalp->dontCombine(true); diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index a4dd10b25..f0f3925e0 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -346,14 +346,10 @@ private: nodep->iterateChildren(*this); // Link to global function if (nodep->formCallTree()) { - if (nodep->name() == "_final") { - UINFO(4, " formCallTree "<fileline(), nodep); - callp->argTypes("vlSymsp"); - m_finalFuncp->addStmtsp(callp); - } else { - nodep->v3fatalSrc("Unknown CFunc name. Make code more generic, with a map of func names"); - } + UINFO(4, " formCallTree "<fileline(), nodep); + callp->argTypes("vlSymsp"); + m_finalFuncp->addStmtsp(callp); } } virtual void visit(AstSenTree* nodep, AstNUser*) { diff --git a/test_regress/t/t_final.pl b/test_regress/t/t_final.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_final.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v new file mode 100644 index 000000000..f8da60810 --- /dev/null +++ b/test_regress/t/t_final.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Charlie Brej. + +module submodule (); + // This bug only appears when not inlining + // verilator no_inline_module + initial begin + $write("d"); + end + final begin + $write("d"); + end +endmodule + +module t (); + generate + for (genvar i = 0; i < 100; i = i + 1) begin : module_set + submodule u_submodule (); + end + endgenerate + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule