Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

Merge branch 'master' into develop-v5

Browse Source
This commit is contained in:
Geza Lore 2022-07-29 12:04:24 +01:00
commit ad2fbfe62d
25 changed files with 472 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changes
View File

@ -27,6 +27,8 @@ Verilator 4.225 devel
* Fix incorrect bit op tree optimization (#3470). [algrobman]
* Fix empty string arguments to display (#3484). [Grulfen]
* Fix table misoptimizing away display (#3488). [Stefan Post]
* Fix wrong bit op tree optimization (#3509). [Nathan Graybeal]
* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
Verilator 4.224 2022-06-19

2
docs/CONTRIBUTORS
View File

@ -33,6 +33,7 @@ Gianfranco Costamagna
Glen Gibb
Graham Rushton
Guokai Chen
Gustav Svensk
Harald Heckmann
Howard Su
Huang Rui
@ -81,6 +82,7 @@ Michaël Lefebvre
Mike Popoloski
Miodrag Milanović
Morten Borup Petersen
Mostafa Gamal
Nandu Raj
Nathan Kohagen
Nathan Myers

18
docs/guide/files.rst
View File

@ -50,7 +50,7 @@ For --cc/--sc, it creates:
- Make include file with class names (from --make gmake)
* - *{prefix}*\ _hier.mk
- Make file for hierarchy blocks (from --make gmake)
* - *{prefix|*\ _hierMkArgs.f
* - *{prefix}*\ _hierMkArgs.f
- Arguments for hierarchical Verilation (from --make gmake)
* - *{prefix}*\ _hierCMakeArgs.f
- Arguments for hierarchical Verilation (from --make cmake)
@ -62,13 +62,17 @@ For --cc/--sc, it creates:
- Top level (SystemVerilog $root) internal header file
* - *{prefix}*\ ___024root.cpp
- Top level (SystemVerilog $root) internal C++ file
* - *{prefix}*___024root*{__n}*\ .cpp
- Additional top level internal C++ files (from --output-split)
* - *{prefix}*\ ___024root\ *{__n}*\ .cpp
- Additional top level internal C++ files
* - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
- Additional top level internal C++ files (hashed to reduce build times)
* - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
- Infrequent cold routines
* - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
* - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
- Infrequent cold routines (hashed to reduce build times)
* - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
- Wave file generation code (from --trace)
* - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
* - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
- Wave file generation code (from --trace)
* - *{prefix}*\ __Dpi.h
- DPI import and export declarations (from --dpi)
@ -87,7 +91,9 @@ For --cc/--sc, it creates:
* - *{prefix}{each_verilog_module}*\ .cpp
- Lower level internal C++ files
* - *{prefix}{each_verilog_module}{__n}*\ .cpp
- Additional lower C++ files (from --output-split)
- Additional lower C++ files
* - *{prefix}{each_verilog_module}{__DepSet_hash__n}*\ .cpp
- Additional lower C++ files (hased to reduce build times)
For --hierarchy mode, it creates:

5
include/verilated.cpp
View File

@ -1459,11 +1459,12 @@ void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...) VL_MT_SAFE {
void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, ...) VL_MT_SAFE {
if (obits_ignored) {}
output = "";
std::string temp_output;
va_list ap;
va_start(ap, formatp);
_vl_vsformat(output, formatp, ap);
_vl_vsformat(temp_output, formatp, ap);
va_end(ap);
output = temp_output;
}
std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE {

4
src/V3AstNodes.h
View File

@ -6127,7 +6127,9 @@ public:
class AstCLog2 final : public AstNodeUniop {
public:
AstCLog2(FileLine* fl, AstNode* lhsp)
: ASTGEN_SUPER_CLog2(fl, lhsp) {}
: ASTGEN_SUPER_CLog2(fl, lhsp) {
dtypeSetSigned32();
}
ASTNODE_NODE_FUNCS(CLog2)
virtual void numberOperate(V3Number& out, const V3Number& lhs) override { out.opCLog2(lhs); }
virtual string emitVerilog() override { return "%f$clog2(%l)"; }

46
src/V3Const.cpp
View File

@ -566,9 +566,35 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
const AstConst* const constp = VN_CAST(lhsp, Const);
CONST_BITOP_RETURN_IF(!constp, nodep->lhsp());
const bool maskFlip = isOrTree();
const V3Number& compNum = constp->num();
auto setPolarities = [this, &compNum](const LeafInfo& ref, const V3Number* maskp) {
const bool maskFlip = isOrTree();
int constantWidth = compNum.width();
if (maskp) constantWidth = std::max(constantWidth, maskp->width());
const int maxBitIdx = std::max(ref.lsb() + constantWidth, ref.msb() + 1);
// Mark all bits checked by this comparison
for (int bitIdx = ref.lsb(); bitIdx < maxBitIdx; ++bitIdx) {
const int maskIdx = bitIdx - ref.lsb();
const bool mask0 = maskp && maskp->bitIs0(maskIdx);
const bool outOfRange = bitIdx > ref.msb();
if (mask0 || outOfRange) { // RHS is 0
if (compNum.bitIs1(maskIdx)) {
// LHS is 1
// And tree: 1 == 0 => always false, set v && !v
// Or tree : 1 != 0 => always true, set v || !v
m_bitPolarities.emplace_back(ref, true, 0);
m_bitPolarities.emplace_back(ref, false, 0);
break;
} else { // This bitIdx is irrelevant
continue;
}
}
const bool polarity = compNum.bitIs1(maskIdx) != maskFlip;
m_bitPolarities.emplace_back(ref, polarity, bitIdx);
}
};
if (const AstAnd* const andp = VN_CAST(nodep->rhsp(), And)) { // comp == (mask & v)
const LeafInfo& mask = findLeaf(andp->lhsp(), true);
CONST_BITOP_RETURN_IF(!mask.constp() || mask.lsb() != 0, andp->lhsp());
@ -583,14 +609,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
incrOps(nodep, __LINE__);
incrOps(andp, __LINE__);
// Mark all bits checked by this comparison
const int maxBitIdx = std::min(ref.lsb() + maskNum.width(), ref.msb() + 1);
for (int bitIdx = ref.lsb(); bitIdx < maxBitIdx; ++bitIdx) {
const int maskIdx = bitIdx - ref.lsb();
if (maskNum.bitIs0(maskIdx)) continue;
const bool polarity = compNum.bitIs1(maskIdx) != maskFlip;
m_bitPolarities.emplace_back(ref, polarity, bitIdx);
}
setPolarities(ref, &maskNum);
} else { // comp == v
const LeafInfo& ref = findLeaf(nodep->rhsp(), false);
CONST_BITOP_RETURN_IF(!ref.refp(), nodep->rhsp());
@ -599,13 +618,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
incrOps(nodep, __LINE__);
// Mark all bits checked by this comparison
const int maxBitIdx = std::min(ref.lsb() + compNum.width(), ref.msb() + 1);
for (int bitIdx = ref.lsb(); bitIdx < maxBitIdx; ++bitIdx) {
const int maskIdx = bitIdx - ref.lsb();
const bool polarity = compNum.bitIs1(maskIdx) != maskFlip;
m_bitPolarities.emplace_back(ref, polarity, bitIdx);
}
setPolarities(ref, nullptr);
}
} else {
CONST_BITOP_SET_FAILED("Mixture of different ops cannot be optimized", nodep);
@ -1751,6 +1764,7 @@ private:
lp->rhsp(lrp);
nodep->lhsp(llp);
nodep->rhsp(rlp);
nodep->dtypep(llp->dtypep()); // dtype of Biop is before shift.
VL_DO_DANGLING(rp->deleteTree(), rp);
VL_DO_DANGLING(rrp->deleteTree(), rrp);
// nodep->dumpTree(cout, " repShiftSame_new: ");

2
src/V3FileLine.h
View File

@ -247,7 +247,7 @@ public:
// OPERATORS
void v3errorEnd(std::ostringstream& str, const string& extra = "");
void v3errorEndFatal(std::ostringstream& str);
void v3errorEndFatal(std::ostringstream& str) VL_ATTR_NORETURN;
/// When building an error, prefix for printing continuation lines
/// e.g. information referring to the same FileLine as before
string warnMore() const;

2
src/V3MergeCond.cpp
View File

@ -790,6 +790,8 @@ private:
// otherwise end the current merge. Return ture if added, false if ended merge.
bool addIfHelpfulElseEndMerge(AstNodeStmt* nodep) {
UASSERT_OBJ(m_mgFirstp, nodep, "List must be open");
if (!checkOrMakeMergeable(nodep)) return false;
if (!m_mgFirstp) return false; // If 'checkOrMakeMergeable' closed the list
if (m_mgNextp == nodep) {
if (isSimplifiableNode(nodep)) {
if (addToList(nodep, nullptr)) return true;

4
src/V3Options.cpp
View File

@ -1010,11 +1010,11 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
if (!strcmp(valp, "clang")) {
m_compLimitBlocks = 80; // limit unknown
m_compLimitMembers = 64; // soft limit, has slowdown bug as of clang++ 3.8
m_compLimitParens = 80; // limit unknown
m_compLimitParens = 240; // controlled by -fbracket-depth, which defaults to 256
} else if (!strcmp(valp, "gcc")) {
m_compLimitBlocks = 0; // Bug free
m_compLimitMembers = 64; // soft limit, has slowdown bug as of g++ 7.1
m_compLimitParens = 0; // Bug free
m_compLimitParens = 240; // Unlimited, but generate same code as for clang
} else if (!strcmp(valp, "msvc")) {
m_compLimitBlocks = 80; // 128, but allow some room
m_compLimitMembers = 0; // probably ok, and AFAIK doesn't support anon structs

2
src/V3Options.h
View File

@ -315,7 +315,7 @@ private:
int m_compLimitBlocks = 0; // compiler selection; number of nested blocks
int m_compLimitMembers = 64; // compiler selection; number of members in struct before make anon array
int m_compLimitParens = 0; // compiler selection; number of nested parens
int m_compLimitParens = 240; // compiler selection; number of nested parens
string m_bin; // main switch: --bin {binary}
string m_exeName; // main switch: -o {name}

96
src/V3Width.cpp
View File

@ -1248,10 +1248,7 @@ private:
}
}
virtual void visit(AstCLog2* nodep) override {
if (m_vup->prelim()) {
iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH);
nodep->dtypeSetSigned32();
}
if (m_vup->prelim()) { iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH); }
}
virtual void visit(AstPow* nodep) override {
// Pow is special, output sign only depends on LHS sign, but
@ -3564,50 +3561,66 @@ private:
// which member each AstPatMember corresponds to before we can
// determine the dtypep for that PatMember's value, and then
// width the initial value appropriately.
using PatMap = std::map<const AstMemberDType*, AstPatMember*>;
using PatMap = std::map<const AstMemberDType*, AstPatMember*>; // Store member: value
using DTypeMap
= std::map<const std::string, AstPatMember*>; // Store data_type: default_value
PatMap patmap;
DTypeMap dtypemap;
{
const AstMemberDType* memp = vdtypep->membersp();
AstPatMember* patp = VN_CAST(nodep->itemsp(), PatMember);
for (; memp || patp;) {
while (patp) {
do {
if (patp) {
if (patp->keyp()) {
if (const AstText* textp = VN_CAST(patp->keyp(), Text)) {
memp = vdtypep->findMember(textp->text());
if (!memp) {
patp->keyp()->v3error("Assignment pattern key '"
<< textp->text()
<< "' not found as member");
break;
}
if (patp->keyp()) {
// '{member:value} or '{data_type: default_value}
if (const AstText* textp = VN_CAST(patp->keyp(), Text)) {
// member: value
memp = vdtypep->findMember(textp->text());
if (!memp) {
patp->keyp()->v3error("Assignment pattern key '"
<< textp->text() << "' not found as member");
break;
} else {
patp->keyp()->v3error(
"Assignment pattern key not supported/understood: "
<< patp->keyp()->prettyTypeName());
const std::pair<PatMap::iterator, bool> ret
= patmap.emplace(memp, patp);
if (!ret.second) {
patp->v3error("Assignment pattern contains duplicate entry: "
<< VN_AS(patp->keyp(), Text)->text());
}
memp = VN_AS(memp->nextp(), MemberDType);
}
} else if (const AstNodeDType* nodedtypep
= VN_CAST(patp->keyp(), NodeDType)) {
// data_type: default_value
const string dtype = nodedtypep->dtypep()->prettyDTypeName();
auto it = dtypemap.find(dtype);
if (it == dtypemap.end()) {
dtypemap.emplace(dtype, patp);
} else {
// Override stored default_value
it->second = patp->cloneTree(false);
}
} else {
// Undefined pattern
patp->keyp()->v3error(
"Assignment pattern key not supported/understood: "
<< patp->keyp()->prettyTypeName());
}
}
if (memp && !patp) {
// Missing init elements, warn below
memp = nullptr;
patp = nullptr;
break;
} else if (!memp && patp) {
patp->v3error("Assignment pattern contains too many elements");
memp = nullptr;
patp = nullptr;
break;
} else {
const std::pair<PatMap::iterator, bool> ret = patmap.emplace(memp, patp);
if (!ret.second) {
patp->v3error("Assignment pattern contains duplicate entry: "
<< VN_AS(patp->keyp(), Text)->text());
// constant expr
if (memp) {
const std::pair<PatMap::iterator, bool> ret
= patmap.emplace(memp, patp);
if (!ret.second) {
patp->v3error("Assignment pattern contains duplicate entry: "
<< VN_AS(patp->keyp(), Text)->text());
}
memp = VN_AS(memp->nextp(), MemberDType);
}
}
} while (false);
// Next
if (memp) memp = VN_AS(memp->nextp(), MemberDType);
if (patp) patp = VN_AS(patp->nextp(), PatMember);
}
}
@ -3618,13 +3631,22 @@ private:
AstPatMember* newpatp = nullptr;
AstPatMember* patp = nullptr;
if (it == patmap.end()) {
if (defaultp) {
const string memp_DType = memp->virtRefDTypep()->prettyDTypeName();
const auto it2 = dtypemap.find(memp_DType);
if (it2 != dtypemap.end()) {
// default_value for data_type
patp = it2->second;
newpatp = patp->cloneTree(false);
patp = newpatp;
} else if (defaultp) {
// default_value for any unassigned member yet
newpatp = defaultp->cloneTree(false);
patp = newpatp;
} else {
if (!VN_IS(vdtypep, UnionDType)) {
nodep->v3error("Assignment pattern missed initializing elements: "
<< memp->prettyTypeName());
<< memp->virtRefDTypep()->prettyDTypeName() << " "
<< memp->prettyName());
}
}
} else {

1
src/verilog.y
View File

@ -3545,6 +3545,7 @@ patternKey<nodep>: // IEEE: merge structure_pattern_key, array_patt
| yaFLOATNUM { $$ = new AstConst($<fl>1,AstConst::RealDouble(),$1); }
| id { $$ = new AstText($<fl>1,*$1); }
| strAsInt { $$ = $1; }
| simple_type { $$ = $1; }
;
assignment_pattern<patternp>: // ==IEEE: assignment_pattern

13
test_regress/driver.pl
View File

@ -2259,10 +2259,15 @@ sub vcd_identical {
print "\t$cmd\n" if $::Debug;
$out = `$cmd`;
if ($? != 0 || $out ne '') {
print $out;
$self->error("VCD miscompares $fn1 $fn2\n");
$self->copy_if_golden($fn1, $fn2);
return 0;
$cmd = qq{vcddiff "$fn2" "$fn1"};
print "\t$cmd\n" if $::Debug;
$out = `$cmd`;
if ($? != 0 || $out ne '') {
print $out;
$self->error("VCD miscompares $fn2 $fn1\n");
$self->copy_if_golden($fn1, $fn2);
return 0;
}
}
}
{

2
test_regress/t/t_array_list_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: MEMBERDTYPE 't3'
%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: logic t3
: ... In instance t
38 | test_out <= '{'0, '0};
| ^~

9
test_regress/t/t_const_no_opt.pl
View File

@ -13,7 +13,14 @@ top_filename("t/t_const_opt.v");
# Run the same design as t_const_opt.pl without bitopt tree optimization to make sure that the result is same.
compile(
verilator_flags2 => ["-Wno-UNOPTTHREADS", "--stats", "-fno-const-bit-op-tree", "$Self->{t_dir}/t_const_opt.cpp"],
verilator_flags2 => [
"-Wno-UNOPTTHREADS",
"--stats",
"-fno-const-bit-op-tree",
"$Self->{t_dir}/t_const_opt.cpp",
"-CFLAGS",
"-Wno-tautological-compare"
],
);
execute(

2
test_regress/t/t_const_opt.pl
View File

@ -19,7 +19,7 @@ execute(
);
if ($Self->{vlt}) {
file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 14);
file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 15);
}
ok(1);
1;

84
test_regress/t/t_const_opt.v
View File

@ -62,7 +62,7 @@ module t(/*AUTOARG*/
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hde21e019a3e12039
`define EXPECTED_SUM 64'h9366e49d91bfe942
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
@ -87,10 +87,13 @@ module Test(/*AUTOARG*/
logic bug3197_out;
logic bug3445_out;
logic bug3470_out;
logic bug3509_out;
wire bug3399_out0;
wire bug3399_out1;
output logic o;
logic [8:0] tmp;
logic [11:0] tmp;
assign o = ^tmp;
always_ff @(posedge clk) begin
@ -115,12 +118,17 @@ module Test(/*AUTOARG*/
tmp[6] <= bug3197_out;
tmp[7] <= bug3445_out;
tmp[8] <= bug3470_out;
tmp[9] <= bug3509_out;
tmp[10]<= bug3399_out0;
tmp[11]<= bug3399_out1;
end
bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out));
bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out));
bug3445 i_bug3445(.clk(clk), .in(d), .out(bug3445_out));
bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out));
bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out));
bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1));
endmodule
@ -235,3 +243,75 @@ module bug3470(input wire clk, input wire [31:0] in, output wire out);
assign out = tmp;
endmodule
// Bug3509
// Only bit range of "var" was considered in
// "comp == (mask & var)"
// and
// "comp != (mask & var)"
//
// It caused wrong result if "comp" has wider bit width because
// upper bit of "comp" was ignored.
//
// If "comp" has '1' in upper bit range than "var",
// the result is constant after optimization.
module bug3509(input wire clk, input wire [31:0] in, output reg out);
reg [2:0] r0;
always_ff @(posedge clk)
r0 <= in[2:0];
wire [3:0] w1_0 = {1'b0, in[2:0]};
wire [3:0] w1_1 = {1'b0, r0};
wire tmp[4];
// tmp[0:1] is always 0 because w1[3] == 1'b0
// tmp[2:3] is always 1 because w1[3] == 1'b0
assign tmp[0] = w1_0[3:2] == 2'h2 && w1_0[1:0] != 2'd3;
assign tmp[1] = w1_1[3:2] == 2'h2 && w1_1[1:0] != 2'd3;
assign tmp[2] = w1_0[3:2] != 2'h2 || w1_0[1:0] == 2'd3;
assign tmp[3] = w1_1[3:2] != 2'h2 || w1_1[1:0] == 2'd3;
always_ff @(posedge clk) begin
out <= tmp[0] | tmp[1] | !tmp[2] | !tmp[3];
end
always @(posedge clk) begin
if(tmp[0]) begin
$display("tmp[0] != 0");
$stop;
end
if(tmp[1]) begin
$display("tmp[1] != 0");
$stop;
end
if(!tmp[2]) begin
$display("tmp[2] != 1");
$stop;
end
if(!tmp[3]) begin
$display("tmp[3] != 1");
$stop;
end
end
endmodule
// Bug3399
// replaceShiftSame() in V3Const.cpp optimizes
// Or(Shift(ll,CONSTlr),Shift(rl,CONSTrr==lr)) -> Shift(Or(ll,rl),CONSTlr)
// (Or/And may also be reversed)
//
// dtype of Or after the transformation must be as same as ll and rl, but was dtype of Or BEFORE transformation.
// When the result of Shift was 1 bit width, bit op tree optimization
// optimized the tree even though the graph needs more width.
// Remember that the target of bit op tree optimization is 1 bit width.
module bug3399(input wire clk, input wire [31:0] in, inout wire out0, inout wire out1);
logic [1:0] driver = '0;
logic [1:0] d;
always_ff @(posedge clk) begin
driver <= 2'b11;
d <= in[1:0];
end
assign out0 = driver[0] ? d[0] : 1'bz;
assign out1 = driver[1] ? d[1] : 1'bz;
endmodule

20
test_regress/t/t_merge_cond_no_extend.pl Executable file
View File

@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Geza Lore. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt_all => 1);
compile(
verilator_flags2 => ["--stats"],
);
file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, 0);
ok(1);
1;

22
test_regress/t/t_merge_cond_no_extend.v Normal file
View File

@ -0,0 +1,22 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module t (
input wire clk,
input wire [7:0] i,
input wire a,
output reg [7:0] o
);
reg cond = 0;
always @(posedge clk) begin
if (cond) o = i;
cond = a;
if (cond) o = ~i;
end
endmodule

21
test_regress/t/t_structu_dataType_assignment.pl Executable file
View File

@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

137
test_regress/t/t_structu_dataType_assignment.v Normal file
View File

@ -0,0 +1,137 @@
// DESCRIPTION: Verilator: Verilog Test module for specialized type default values
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Mostafa Gamal.
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off UNPACKED */
module top();
typedef struct { // IEEE 1800-2017 SV CH:5.10
int a;
shortint b;
} ab_struct;
typedef struct { // IEEE 1800-2017 SV CH:10.9.2
int x;
int y;
} st_struct;
typedef struct { // IEEE 1800-2017 SV CH:10.9.2
logic [7:0] a;
bit b;
bit signed [31:0] c;
int s;
} sa_struct;
typedef struct { // IEEE 1800-2017 SV CH:10.9.2
int A;
struct {
int B, C;
} BC1, BC2;
} DEF_struct;
// struct ab
ab_struct ab;
ab_struct abkey[1:0];
// struct st
st_struct st;
int k = 1;
// struct sa
sa_struct sa;
// struct DEF
DEF_struct DEF;
initial begin;
// struct ab
ab = '{0, 0}; //constant member by position
if (ab.a != 0) $stop;
if (ab.b != 0) $stop;
ab = '{default: 0}; //default value
if (ab.a != 0) $stop;
if (ab.b != 0) $stop;
ab = '{int: 1, shortint: 0}; //data type and default value
if (ab.a != 1) $stop;
if (ab.b != 0) $stop;
abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value
if (abkey[1].a != 1) $stop;
if (abkey[1].b != 2) $stop;
if (abkey[0].a != 2) $stop;
if (abkey[0].b != 3) $stop;
// struct st
st = '{1, 2+k}; //constant member by position
if (st.x != 1) $stop;
if (st.y != 2+k) $stop;
st = '{x:2, y:3+k}; //member: value
if (st.x != 2) $stop;
if (st.y != 3+k) $stop;
st = '{int:2, int:3+k}; //data_type: value override
if (st.x != 3+k) $stop;
if (st.y != 3+k) $stop;
// struct sa
sa = '{default:'1};
if (sa.a != '1) $stop;
if (sa.b != '1) $stop;
if (sa.c != '1) $stop;
if (sa.s != '1) $stop;
sa = '{default:'1, int: 5};
if (sa.a != '1) $stop;
if (sa.b != '1) $stop;
if (sa.c != '1) $stop;
if (sa.s != 5) $stop;
sa = '{default:'1, int: 5, b: 0};
if (sa.a != '1) $stop;
if (sa.b != 0) $stop;
if (sa.c != '1) $stop;
if (sa.s != 5) $stop;
// struct DEF
DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}};
if (DEF.A != 1) $stop;
if (DEF.BC1.B != 2) $stop;
if (DEF.BC1.C != 3) $stop;
if (DEF.BC2.B != 4) $stop;
if (DEF.BC2.C != 5) $stop;
DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}};
if (DEF.A != 0) $stop;
if (DEF.BC1.B != 10) $stop;
if (DEF.BC1.C != 10) $stop;
if (DEF.BC2.B != 5) $stop;
if (DEF.BC2.C != 5) $stop;
DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}};
if (DEF.A != 1) $stop;
if (DEF.BC1.B != 10) $stop;
if (DEF.BC1.C != 10) $stop;
if (DEF.BC2.B != 5) $stop;
if (DEF.BC2.C != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

5
test_regress/t/t_structu_dataType_assignment_bad.out Normal file
View File

@ -0,0 +1,5 @@
%Error: t/t_structu_dataType_assignment_bad.v:19:26: Assignment pattern key not supported/understood: CONST '?32?sh1'
: ... In instance top
19 | DEF_struct DEF_bad = '{1: 5, default: 10};
| ^
%Error: Exiting due to

21
test_regress/t/t_structu_dataType_assignment_bad.pl Executable file
View File

@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

21
test_regress/t/t_structu_dataType_assignment_bad.v Normal file
View File

@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module for specialized type default values
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Mostafa Gamal.
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off UNPACKED */
module top();
typedef struct { // IEEE 1800-2017 SV CH:10.9.2
int A;
struct {
int B, C;
} BC1, BC2;
} DEF_struct;
DEF_struct DEF_bad = '{1: 5, default: 10};
endmodule

6
test_regress/t/t_sys_sformat.v
View File

@ -83,6 +83,12 @@ module t;
$swriteo(str2, 4'd12);
if (str2 != "14") $stop;
str3 = "foo";
$sformat(str3, "%s", str3); // $sformat twice so verilator does not
$sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo")
`ifdef TEST_VERBOSE $display("str3=%0s", str3); `endif
if (str3 != "foo") $stop;
$write("*-* All Finished *-*\n");
$finish;
end