forked from github/verilator
parent
c03affa544
commit
a3ff375ce7
@ -29,6 +29,7 @@ Driss Hafdi
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Edgar E. Iglesias
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Eric Rippey
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Fan Shupei
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Felix Neumärker
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Felix Yan
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Garrett Smith
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Geza Lore
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@ -515,7 +515,9 @@ private:
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flp,
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new AstMulD{flp, valuep,
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new AstConst{flp, AstConst::RealDouble{}, m_timescaleFactor}}};
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valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
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} else {
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valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
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valuep = new AstMul{flp, valuep,
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new AstConst{flp, AstConst::Unsized64{},
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static_cast<uint64_t>(m_timescaleFactor)}};
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@ -1952,14 +1952,8 @@ private:
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newp = new AstIToRD{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
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}
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} else if (!basicp->isDouble() && nodep->fromp()->isDouble()) {
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if (basicp->isSigned()) {
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newp
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= new AstRToIRoundS{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
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} else {
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newp = new AstUnsigned{
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nodep->fileline(),
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new AstRToIS{nodep->fileline(), nodep->fromp()->unlinkFrBack()}};
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}
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newp = new AstRToIRoundS{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
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newp->dtypeChgSigned(basicp->isSigned());
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} else if (basicp->isSigned() && !nodep->fromp()->isSigned()) {
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newp = new AstSigned{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
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} else if (!basicp->isSigned() && nodep->fromp()->isSigned()) {
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10
test_regress/t/t_timing_wait_long.out
Normal file
10
test_regress/t/t_timing_wait_long.out
Normal file
@ -0,0 +1,10 @@
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Current realtime: 5000000 == 5000000000
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Current realtime: 10000001 == 10000001
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Current realtime: 15000000 == 15000000
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FULL_TIME: 5000000.000000
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Current realtime: 20000000 == 20000000
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FIT_TIME: 5000000 -- 5000000.000000
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Current realtime: 25000000 == 25000000
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TRUNCATED_TIME: 805696 -- 805696.000000
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Current realtime: 25805696 == 25805696
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*-* All Finished *-*
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28
test_regress/t/t_timing_wait_long.pl
Executable file
28
test_regress/t/t_timing_wait_long.pl
Executable file
@ -0,0 +1,28 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Antmicro Ltd. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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if (!$Self->have_coroutines) {
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skip("No coroutine support");
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}
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else {
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compile(
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verilator_flags2 => ["--exe --main --timing"],
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make_main => 0,
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);
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execute(
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check_finished => 1,
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expect_filename => $Self->{golden_filename},
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);
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}
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ok(1);
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1;
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46
test_regress/t/t_timing_wait_long.v
Normal file
46
test_regress/t/t_timing_wait_long.v
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@ -0,0 +1,46 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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module timing_wait_long();
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localparam real FULL_TIME = 5e6;
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/* verilator lint_off WIDTHTRUNC */
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localparam [22:0] FIT_TIME = int'(5e6);
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localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696
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/* verilator lint_on WIDTHTRUNC */
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real realvar_time = 5e6;
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time timevar;
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initial begin
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#5ms;
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$display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9));
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realvar_time = realvar_time + 1;
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#realvar_time;
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$display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1));
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timevar = time'(realvar_time - 2);
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#timevar;
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$display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6));
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$display("FULL_TIME: %f", FULL_TIME);
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#FULL_TIME;
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$display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6));
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$display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME));
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#FIT_TIME;
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$display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6));
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$display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME));
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#TRUNCATED_TIME;
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$display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6 + real'(int'(5e6) % 2**22)));
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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