From a3ff375ce7853a9e376ad73ac4795c54d79222e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Neum=C3=A4rker?= <34678034+xdch47@users.noreply.github.com> Date: Tue, 28 Feb 2023 03:42:22 +0100 Subject: [PATCH] Fix timing delays to not truncate below 64 bits (#3973) (#3982) --- docs/CONTRIBUTORS | 1 + src/V3Timing.cpp | 2 ++ src/V3Width.cpp | 10 ++---- test_regress/t/t_timing_wait_long.out | 10 ++++++ test_regress/t/t_timing_wait_long.pl | 28 ++++++++++++++++ test_regress/t/t_timing_wait_long.v | 46 +++++++++++++++++++++++++++ 6 files changed, 89 insertions(+), 8 deletions(-) create mode 100644 test_regress/t/t_timing_wait_long.out create mode 100755 test_regress/t/t_timing_wait_long.pl create mode 100644 test_regress/t/t_timing_wait_long.v diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index ee8a4c5a0..ecde8cdba 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -29,6 +29,7 @@ Driss Hafdi Edgar E. Iglesias Eric Rippey Fan Shupei +Felix Neumärker Felix Yan Garrett Smith Geza Lore diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index 2b16ff972..0a096661e 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -515,7 +515,9 @@ private: flp, new AstMulD{flp, valuep, new AstConst{flp, AstConst::RealDouble{}, m_timescaleFactor}}}; + valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); } else { + valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); valuep = new AstMul{flp, valuep, new AstConst{flp, AstConst::Unsized64{}, static_cast(m_timescaleFactor)}}; diff --git a/src/V3Width.cpp b/src/V3Width.cpp index ab945565c..ab815b617 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1952,14 +1952,8 @@ private: newp = new AstIToRD{nodep->fileline(), nodep->fromp()->unlinkFrBack()}; } } else if (!basicp->isDouble() && nodep->fromp()->isDouble()) { - if (basicp->isSigned()) { - newp - = new AstRToIRoundS{nodep->fileline(), nodep->fromp()->unlinkFrBack()}; - } else { - newp = new AstUnsigned{ - nodep->fileline(), - new AstRToIS{nodep->fileline(), nodep->fromp()->unlinkFrBack()}}; - } + newp = new AstRToIRoundS{nodep->fileline(), nodep->fromp()->unlinkFrBack()}; + newp->dtypeChgSigned(basicp->isSigned()); } else if (basicp->isSigned() && !nodep->fromp()->isSigned()) { newp = new AstSigned{nodep->fileline(), nodep->fromp()->unlinkFrBack()}; } else if (!basicp->isSigned() && nodep->fromp()->isSigned()) { diff --git a/test_regress/t/t_timing_wait_long.out b/test_regress/t/t_timing_wait_long.out new file mode 100644 index 000000000..a75a6bc67 --- /dev/null +++ b/test_regress/t/t_timing_wait_long.out @@ -0,0 +1,10 @@ +Current realtime: 5000000 == 5000000000 +Current realtime: 10000001 == 10000001 +Current realtime: 15000000 == 15000000 +FULL_TIME: 5000000.000000 +Current realtime: 20000000 == 20000000 +FIT_TIME: 5000000 -- 5000000.000000 +Current realtime: 25000000 == 25000000 +TRUNCATED_TIME: 805696 -- 805696.000000 +Current realtime: 25805696 == 25805696 +*-* All Finished *-* diff --git a/test_regress/t/t_timing_wait_long.pl b/test_regress/t/t_timing_wait_long.pl new file mode 100755 index 000000000..42423c59c --- /dev/null +++ b/test_regress/t/t_timing_wait_long.pl @@ -0,0 +1,28 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Antmicro Ltd. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_coroutines) { + skip("No coroutine support"); +} +else { + compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + + execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); +} +ok(1); +1; diff --git a/test_regress/t/t_timing_wait_long.v b/test_regress/t/t_timing_wait_long.v new file mode 100644 index 000000000..c9417b913 --- /dev/null +++ b/test_regress/t/t_timing_wait_long.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +`timescale 1ns/1ps + +module timing_wait_long(); + localparam real FULL_TIME = 5e6; + /* verilator lint_off WIDTHTRUNC */ + localparam [22:0] FIT_TIME = int'(5e6); + localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696 + /* verilator lint_on WIDTHTRUNC */ + + real realvar_time = 5e6; + time timevar; + initial begin + #5ms; + $display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9)); + + realvar_time = realvar_time + 1; + #realvar_time; + $display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1)); + + timevar = time'(realvar_time - 2); + #timevar; + $display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6)); + + $display("FULL_TIME: %f", FULL_TIME); + #FULL_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6)); + + $display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME)); + #FIT_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6)); + + $display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME)); + #TRUNCATED_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6 + real'(int'(5e6) % 2**22))); + + $write("*-* All Finished *-*\n"); + $finish(); + end + +endmodule