forked from github/verilator
Fix concats with wide width, bug1088 continued.
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@ -144,8 +144,12 @@ private:
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&& nodep->firstAbovep()->castNodeAssign()
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&& assignNoTemp(nodep->firstAbovep()->castNodeAssign())) {
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// Not much point if it's just a direct assignment to a constant
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} else if (nodep->backp()->castSel()
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&& nodep->backp()->castSel()->widthp() == nodep) {
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// AstSel::width must remain a constant
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} else if (nodep->firstAbovep()
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&& nodep->firstAbovep()->castArraySel()) { // ArraySel's are pointer refs, ignore
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&& nodep->firstAbovep()->castArraySel()) {
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// ArraySel's are pointer refs, ignore
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} else {
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UINFO(4,"Cre Temp: "<<nodep<<endl);
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createDeepTemp(nodep, false);
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18
test_regress/t/t_param_seg.pl
Executable file
18
test_regress/t/t_param_seg.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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28
test_regress/t/t_param_seg.v
Normal file
28
test_regress/t/t_param_seg.v
Normal file
@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Mandy Xu.
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// verilator lint_off WIDTH
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//bug1088
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module t (/*AUTOARG*/
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// Outputs
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err_count,
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// Inputs
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clk, syndromes
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);
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input clk;
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input [7:0] syndromes;
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output reg [1:0] err_count = 0;
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localparam [95:0] M = 96'h4;
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wire [3:0] syn1 = syndromes[0+:M];
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always @(posedge clk) begin
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err_count <= {1'b0, |syn1};
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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