diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index e5e90679a..79c22f86a 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -144,8 +144,12 @@ private:
 			   && nodep->firstAbovep()->castNodeAssign()
 			   && assignNoTemp(nodep->firstAbovep()->castNodeAssign())) {
 		    // Not much point if it's just a direct assignment to a constant
+		} else if (nodep->backp()->castSel()
+			   && nodep->backp()->castSel()->widthp() == nodep) {
+		    // AstSel::width must remain a constant
 		} else if (nodep->firstAbovep()
-			   && nodep->firstAbovep()->castArraySel()) {  // ArraySel's are pointer refs, ignore
+			   && nodep->firstAbovep()->castArraySel()) {
+		    // ArraySel's are pointer refs, ignore
 		} else {
 		    UINFO(4,"Cre Temp: "<<nodep<<endl);
 		    createDeepTemp(nodep, false);
diff --git a/test_regress/t/t_param_seg.pl b/test_regress/t/t_param_seg.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_param_seg.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_seg.v b/test_regress/t/t_param_seg.v
new file mode 100644
index 000000000..1b878032e
--- /dev/null
+++ b/test_regress/t/t_param_seg.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Mandy Xu.
+
+// verilator lint_off WIDTH
+
+//bug1088
+
+module t (/*AUTOARG*/
+   // Outputs
+   err_count,
+   // Inputs
+   clk, syndromes
+   );
+
+   input clk;
+   input [7:0] syndromes;
+   output reg [1:0]  err_count = 0;
+
+   localparam [95:0] M = 96'h4;
+   wire [3:0] syn1 = syndromes[0+:M];
+   always @(posedge clk) begin
+      err_count <= {1'b0, |syn1};
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule