Fix $isunknown with constant Zs.

Changes

@@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix +: and -: on unpacked arrays. (#2304) [engr248]
 
+****  Fix $isunknown with constant Z's.
+
 
 * Verilator 4.034 2020-05-03
 

src/V3Case.cpp

@@ -96,7 +96,7 @@ private:
             } else if (VN_IS(m_caseExprp, Case)
                        && (VN_CAST(m_caseExprp, Case)->casez()
                            || VN_CAST(m_caseExprp, Case)->caseInside())) {
-                if (nodep->num().isUnknown()) {
+                if (nodep->num().isAnyX()) {
                     nodep->v3warn(CASEWITHX, "Use of x constant in casez statement, "
                                              "(perhaps intended ?/z in constant)");
                 }
@@ -460,7 +460,7 @@ private:
         // Xs in case or casez are impossible due to two state simulations
         if (casep->casex()) {
         } else if (casep->casez() || casep->caseInside()) {
-            if (itemp->num().isUnknown()) return true;
+            if (itemp->num().isAnyX()) return true;
         } else {
             if (itemp->num().isFourState()) return true;
         }

src/V3Number.cpp

@@ -912,13 +912,20 @@ bool V3Number::isFourState() const {
     }
     return false;
 }
-bool V3Number::isUnknown() const {
+bool V3Number::isAnyX() const {
     if (isDouble() || isString()) return false;
     for (int bit = 0; bit < width(); bit++) {
         if (bitIsX(bit)) return true;
     }
     return false;
 }
+bool V3Number::isAnyXZ() const {
+    if (isDouble() || isString()) return false;
+    for (int bit = 0; bit < width(); bit++) {
+        if (bitIsX(bit) || bitIsZ(bit)) return true;
+    }
+    return false;
+}
 bool V3Number::isLt(const V3Number& rhs) const {
     for (int bit = 0; bit < std::max(this->width(), rhs.width()); bit++) {
         if (this->bitIs1(bit) && rhs.bitIs0(bit)) { return 1; }
@@ -1099,7 +1106,7 @@ V3Number& V3Number::opCountOnes(const V3Number& lhs) {
 }
 V3Number& V3Number::opIsUnknown(const V3Number& lhs) {
     NUM_ASSERT_OP_ARGS1(lhs);
-    return setSingleBits(lhs.isUnknown());
+    return setSingleBits(lhs.isAnyXZ());
 }
 V3Number& V3Number::opOneHot(const V3Number& lhs) {
     NUM_ASSERT_OP_ARGS1(lhs);

src/V3Number.h

@@ -270,7 +270,8 @@ public:
     bool isLt(const V3Number& rhs) const;  // operator<
     bool isLtXZ(const V3Number& rhs) const;  // operator< with XZ compared
     void isSigned(bool ssigned) { m_signed = ssigned; }
-    bool isUnknown() const;
+    bool isAnyX() const;
+    bool isAnyXZ() const;
     bool isMsbXZ() const { return bitIsXZ(m_width); }
     uint32_t toUInt() const;
     vlsint32_t toSInt() const;

test_regress/t/t_EXAMPLE.v

@@ -16,82 +16,20 @@
 // any use, without warranty, 2020 ____YOUR_NAME_HERE____.
 // SPDX-License-Identifier: CC0-1.0
 
-module t(/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
+module t(/*AUTOARG*/);
 
-   integer cyc=0;
-   reg [63:0] crc;
-   reg [63:0] sum;
-
-   // Take CRC data and apply to testblock inputs
-   wire [31:0] in = crc[31:0];
-
-   /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [31:0]          out;                    // From test of Test.v
-   // End of automatics
-
-   Test test(/*AUTOINST*/
-             // Outputs
-             .out                       (out[31:0]),
-             // Inputs
-             .clk                       (clk),
-             .in                        (in[31:0]));
-
-   // Aggregate outputs into a single result vector
-   wire [63:0] result = {32'h0, out};
-
-   // Test loop
-   always @ (posedge clk) begin
-`ifdef TEST_VERBOSE
-      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
-`endif
-      cyc <= cyc + 1;
-      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
-      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
-      if (cyc == 0) begin
-         // Setup
-         crc <= 64'h5aef0c8d_d70a4497;
-         sum <= '0;
-      end
-      else if (cyc < 10) begin
-         sum <= '0;
-      end
-      else if (cyc < 90) begin
-      end
-      else if (cyc == 99) begin
-         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
-         if (crc !== 64'hc77bb9b3784ea091) $stop;
-         // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h4afe43fb79d7b71e
-         if (sum !== `EXPECTED_SUM) $stop;
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
+   initial begin
+      // verilator lint_off WIDTH
+      parameter [3:0] val0 = 32'b000x;
+      parameter [3:0] val1 = 32'b000z;
+      parameter [3:0] val2 = 32'b00xz;
+      parameter [3:0] val3 = 32'b0000;
+      $display(":assert: (%d == 1)", $isunknown(val0));
+      $display(":assert: (%d == 1)", $isunknown(val1));
+      $display(":assert: (%d == 1)", $isunknown(val2));
+      $display(":assert: (%d == 0)", $isunknown(val3));
+      $write("*-* All Finished *-*\n");
+      $finish;
    end
 
 endmodule
-
-module Test(/*AUTOARG*/
-   // Outputs
-   out,
-   // Inputs
-   clk, in
-   );
-
-   // Replace this module with the device under test.
-   //
-   // Change the code in the t module to apply values to the inputs and
-   // merge the output values into the result vector.
-
-   input clk;
-   input [31:0] in;
-   output reg [31:0] out;
-
-   always @(posedge clk) begin
-      out <= in;
-   end
-endmodule

test_regress/t/t_math_svl.v

@@ -135,6 +135,13 @@ module t (/*AUTOARG*/
       end
    end
 
+   initial begin
+      if ($isunknown(4'b000x) !== 1'b1) $stop;
+      if ($isunknown(4'b000z) !== 1'b1) $stop;
+      if ($isunknown(4'b00xz) !== 1'b1) $stop;
+      if ($isunknown(4'b0000) !== 1'b0) $stop;
+   end
+
    final begin
       $write("Goodbye world, at cycle %0d\n", cyc);
    end