From 4f32b093e6e237ee11bdcda44f07c66d0f1cbe4a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 7 May 2020 18:11:06 -0400 Subject: [PATCH 1/3] Commentary --- docs/install.adoc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/docs/install.adoc b/docs/install.adoc index 51731a0e5..61d665091 100644 --- a/docs/install.adoc +++ b/docs/install.adoc @@ -80,8 +80,7 @@ MSVC++. To build or run Verilator you need these standard packages: - sudo apt-get install perl python3 - sudo apt-get install make + sudo apt-get install perl python3 make sudo apt-get install g++ # Alternatively, clang sudo apt-get install libgz # Non-Ubuntu (ignore if gives error) sudo apt-get install libfl2 libfl-dev zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) @@ -95,12 +94,11 @@ good performance: To build Verilator you will need to install these packages; these do not need to be present to run Verilator: - sudo apt-get install git - sudo apt-get install autoconf flex bison + sudo apt-get install git autoconf flex bison Those developing Verilator itself may also want these (see internals.adoc): - sudo apt-get install gdb asciidoctor graphviz cmake clang-format + sudo apt-get install gdb asciidoctor graphviz cmake clang clang-format gprof cpan install Pod::Perldoc cpan install Unix::Processors cpan install Parallel::Forker From b56a25e89cb1ddb9486db80988e78182ea3d3e68 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 7 May 2020 18:21:02 -0400 Subject: [PATCH 2/3] Fix newish error to use standard parens to ref IEEE. --- src/V3Width.cpp | 6 +++--- test_regress/t/t_timing_func_bad.out | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 51a9922db..382160da3 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -540,13 +540,13 @@ private: } virtual void visit(AstDelay* nodep) VL_OVERRIDE { if (VN_IS(m_procedurep, Final)) { - nodep->v3error("Delays are not legal in final blocks. IEEE 1800-2017 9.2.3"); + nodep->v3error("Delays are not legal in final blocks (IEEE 1800-2017 9.2.3)"); VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); return; } if (VN_IS(m_ftaskp, Func)) { - nodep->v3error("Delays are not legal in functions. Suggest use a task. " - "IEEE 1800-2017 13.4.4"); + nodep->v3error("Delays are not legal in functions. Suggest use a task " + "(IEEE 1800-2017 13.4.4)"); VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); return; } diff --git a/test_regress/t/t_timing_func_bad.out b/test_regress/t/t_timing_func_bad.out index 681f70631..978f09039 100644 --- a/test_regress/t/t_timing_func_bad.out +++ b/test_regress/t/t_timing_func_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_timing_func_bad.v:10:8: Delays are not legal in functions. Suggest use a task. IEEE 1800-2017 13.4.4 +%Error: t/t_timing_func_bad.v:10:8: Delays are not legal in functions. Suggest use a task (IEEE 1800-2017 13.4.4) : ... In instance t 10 | #1 $stop; | ^ -%Error: t/t_timing_func_bad.v:23:8: Delays are not legal in final blocks. IEEE 1800-2017 9.2.3 +%Error: t/t_timing_func_bad.v:23:8: Delays are not legal in final blocks (IEEE 1800-2017 9.2.3) : ... In instance t 23 | #1; | ^ From 5f7ae1fbcef3691c50f242fce24333740992660e Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 7 May 2020 21:04:26 -0400 Subject: [PATCH 3/3] wip --- src/V3Case.cpp | 4 +- src/V3Number.cpp | 11 ++++- src/V3Number.h | 3 +- test_regress/t/t_EXAMPLE.v | 88 ++++++------------------------------- test_regress/t/t_math_svl.v | 7 +++ 5 files changed, 33 insertions(+), 80 deletions(-) diff --git a/src/V3Case.cpp b/src/V3Case.cpp index e125afcd7..949908a98 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -96,7 +96,7 @@ private: } else if (VN_IS(m_caseExprp, Case) && (VN_CAST(m_caseExprp, Case)->casez() || VN_CAST(m_caseExprp, Case)->caseInside())) { - if (nodep->num().isUnknown()) { + if (nodep->num().isAnyX()) { nodep->v3warn(CASEWITHX, "Use of x constant in casez statement, " "(perhaps intended ?/z in constant)"); } @@ -460,7 +460,7 @@ private: // Xs in case or casez are impossible due to two state simulations if (casep->casex()) { } else if (casep->casez() || casep->caseInside()) { - if (itemp->num().isUnknown()) return true; + if (itemp->num().isAnyX()) return true; } else { if (itemp->num().isFourState()) return true; } diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 2c6491845..d23800e08 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -912,13 +912,20 @@ bool V3Number::isFourState() const { } return false; } -bool V3Number::isUnknown() const { +bool V3Number::isAnyX() const { if (isDouble() || isString()) return false; for (int bit = 0; bit < width(); bit++) { if (bitIsX(bit)) return true; } return false; } +bool V3Number::isAnyXZ() const { + if (isDouble() || isString()) return false; + for (int bit = 0; bit < width(); bit++) { + if (bitIsX(bit) || bitIsZ(bit)) return true; + } + return false; +} bool V3Number::isLt(const V3Number& rhs) const { for (int bit = 0; bit < std::max(this->width(), rhs.width()); bit++) { if (this->bitIs1(bit) && rhs.bitIs0(bit)) { return 1; } @@ -1099,7 +1106,7 @@ V3Number& V3Number::opCountOnes(const V3Number& lhs) { } V3Number& V3Number::opIsUnknown(const V3Number& lhs) { NUM_ASSERT_OP_ARGS1(lhs); - return setSingleBits(lhs.isUnknown()); + return setSingleBits(lhs.isAnyXZ()); } V3Number& V3Number::opOneHot(const V3Number& lhs) { NUM_ASSERT_OP_ARGS1(lhs); diff --git a/src/V3Number.h b/src/V3Number.h index 432fe8af4..016796dcb 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -270,7 +270,8 @@ public: bool isLt(const V3Number& rhs) const; // operator< bool isLtXZ(const V3Number& rhs) const; // operator< with XZ compared void isSigned(bool ssigned) { m_signed = ssigned; } - bool isUnknown() const; + bool isAnyX() const; + bool isAnyXZ() const; bool isMsbXZ() const { return bitIsXZ(m_width); } uint32_t toUInt() const; vlsint32_t toSInt() const; diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index 4e1051614..c3667e195 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -16,82 +16,20 @@ // any use, without warranty, 2020 ____YOUR_NAME_HERE____. // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t(/*AUTOARG*/); - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics - - Test test(/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); - - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, out}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // verilator lint_off WIDTH + parameter [3:0] val0 = 32'b000x; + parameter [3:0] val1 = 32'b000z; + parameter [3:0] val2 = 32'b00xz; + parameter [3:0] val3 = 32'b0000; + $display(":assert: (%d == 1)", $isunknown(val0)); + $display(":assert: (%d == 1)", $isunknown(val1)); + $display(":assert: (%d == 1)", $isunknown(val2)); + $display(":assert: (%d == 0)", $isunknown(val3)); + $write("*-* All Finished *-*\n"); + $finish; end endmodule - -module Test(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); - - // Replace this module with the device under test. - // - // Change the code in the t module to apply values to the inputs and - // merge the output values into the result vector. - - input clk; - input [31:0] in; - output reg [31:0] out; - - always @(posedge clk) begin - out <= in; - end -endmodule diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 6ece121c7..e7d93720a 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -135,6 +135,13 @@ module t (/*AUTOARG*/ end end + initial begin + if ($isunknown(4'b000x) !== 1'b1) $stop; + if ($isunknown(4'b000z) !== 1'b1) $stop; + if ($isunknown(4'b00xz) !== 1'b1) $stop; + if ($isunknown(4'b0000) !== 1'b0) $stop; + end + final begin $write("Goodbye world, at cycle %0d\n", cyc); end