forked from github/verilator
Remove test_vcs directory.
This commit is contained in:
Wilson Snyder
parent
d33ad7600b
commit
903ee0622d
@ -100,7 +100,7 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
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SHELL = /bin/sh
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SUBDIRS = src test_verilated test_c test_sc test_sp test_regress test_vcs
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SUBDIRS = src test_verilated test_c test_sc test_sp test_regress
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INFOS = README README.html README.pdf internals.txt internals.html \
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internals.pdf verilator.txt verilator.html verilator.1 verilator.pdf
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@ -183,7 +183,7 @@ msg_test: all_nomsg
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.PHONY:test
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ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users
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test: test_vcs test_c test_sc test_sp test_verilated test_regress
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test: test_c test_sc test_sp test_verilated test_regress
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else
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test: test_c test_sc test_sp
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endif
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@ -192,8 +192,6 @@ endif
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@echo "Type 'make install' to install documentation."
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@echo
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test_vcs: all_nomsg
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@(cd test_vcs && $(MAKE))
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test_c: all_nomsg
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@(cd test_c && $(MAKE))
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test_c_debug: all_nomsg
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@ -637,7 +637,6 @@ INPUT = doxygen-mainpage \
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test_sc \
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test_sp \
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test_v \
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test_vcs \
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test_verilated
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# This tag can be used to specify the character encoding of the source files
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@ -474,7 +474,7 @@ be warning free.
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=item --enable-longtests
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In addition to the standard C, SystemC and SystemPerl tests also run the
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tests in the C<test_vcs>, C<test_verilated> and C<test_regress> directories
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tests in the C<test_verilated> and C<test_regress> directories
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when using I<make test>. This is disabled by default as SystemC/SystemPerl
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installation problems would otherwise falsely indicate a Verilator problem.
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@ -199,7 +199,6 @@ The directories in the kit after de-taring are as follows:
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test_c => Example Verilog->C++ conversion
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test_sc => Example Verilog->SystemC conversion
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test_sp => Example Verilog->SystemPerl conversion
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test_vcs => Example Verilog->VCS conversion (test the test)
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test_verilated => Internal tests
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test_regress => Internal tests
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13
test_vcs/.gitignore
vendored
13
test_vcs/.gitignore
vendored
@ -1,13 +0,0 @@
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*.old
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*.dmp
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*.log
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*.csrc
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*.vcd
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csrc
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vcs.key
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ucli.key
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*.daidir
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simv
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obj_*
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project
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INCA_libs
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@ -1,76 +0,0 @@
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#*****************************************************************************
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#
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# DESCRIPTION: Verilator Example: Makefile for inside source directory
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#
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# This calls the object directory makefile. That allows the objects to
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# be placed in the "current directory" which simplifies the Makefile.
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#
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# Copyright 2003-2014 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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#
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#****************************************************************************/
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default: test
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# This must point to the root of the VERILATOR kit
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VERILATOR_ROOT := $(shell pwd)/..
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export VERILATOR_ROOT
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# Pick up PERL and other variable settings
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include $(VERILATOR_ROOT)/include/verilated.mk
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######################################################################
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V_FILES := $(wildcard *.v ../test_v/*.v)
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######################################################################
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ifneq ($(VCS_HOME),)
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test:: vcs
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else
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test:: novcs
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endif
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ifneq ($(NC_ROOT),)
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test:: nc
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else
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test:: nonc
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endif
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######################################################################
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novcs:
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@echo "No VCS simulator installed."
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@echo "Not running VCS regression test."
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vcs: vcs_passed.log
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simv: $(V_FILES) ../test_v/input.vc
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vcs +cli -I -sverilog +define+VCS+1 -f ../test_v/input.vc -q bench.v
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vcs_passed.log : simv
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-rm -f test_passed.log
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./simv -l sim.log
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grep -q Finished sim.log && grep Finished sim.log > vcs_passed.log
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######################################################################
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nonc:
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@echo "No NC-Verilog simulator installed."
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@echo "Not running NC-Verilog regression test."
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nc: nc_passed.log
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nc_passed.log: $(V_FILES) ../test_v/input.vc
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ncverilog +define+ncverilog=1 +licqueue -f ../test_v/input.vc -q bench.v
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-rm -f nc_passed.log
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grep -q Finished ncverilog.log && grep Finished ncverilog.log > nc_passed.log
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######################################################################
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maintainer-copy::
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clean mostlyclean distclean maintainer-clean::
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-rm -rf obj_dir *.log *.dmp *.vpd simv* *.key csrc INCA_libs
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@ -1,81 +0,0 @@
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// DESCRIPTION: Verilator Test: Top level testbench for VCS or other fully Verilog compliant simulators
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`timescale 1 ns / 1ns
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module bench;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [39:0] out_quad; // From top of top.v
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wire [1:0] out_small; // From top of top.v
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wire [69:0] out_wide; // From top of top.v
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wire passed; // From top of top.v
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// End of automatics
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reg clk;
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reg fastclk;
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reg reset_l;
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reg [1:0] in_small;
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reg [39:0] in_quad;
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reg [69:0] in_wide;
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// Test cases
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top top (/*AUTOINST*/
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// Outputs
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.passed (passed),
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.out_small (out_small[1:0]),
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.out_quad (out_quad[39:0]),
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.out_wide (out_wide[69:0]),
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// Inputs
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.clk (clk),
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.fastclk (fastclk),
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.reset_l (reset_l),
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.in_small (in_small[1:0]),
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.in_quad (in_quad[39:0]),
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.in_wide (in_wide[69:0]));
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//surefire lint_off STMINI
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//surefire lint_off STMFVR
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//surefire lint_off DLYONE
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integer fh;
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// surefire lint_off CWECBB
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initial begin
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reset_l = 1'b1; // Want to catch negedge
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fastclk = 0;
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clk = 0;
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forever begin
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in_small = 0;
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in_wide = 0;
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$write("[%0t] %x %x %x %x %x\n", $time, clk, reset_l, passed, out_small, out_wide);
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if (($time % 10) == 3) clk = 1'b1;
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if (($time % 10) == 8) clk = 1'b0;
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if ($time>10) reset_l = 1'b1;
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else if ($time > 1) reset_l = 1'b0;
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if ($time>60 || passed === 1'b1) begin
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if (passed !== 1'b1) begin
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$write("A Test failed!!!\n");
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$stop;
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end
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else begin
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$write("*-* All Finished *-*\n"); // Magic if using perl's Log::Detect
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fh = $fopen("test_passed.log");
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$fclose(fh);
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end
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$finish;
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end
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#1;
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fastclk = !fastclk;
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end
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end
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../test_v")
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// compile-command: "vlint --brief -f ../test_v/input.vc bench.v"
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// End:
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