From 903ee0622d18dd75f0eb1fc45cfe2f4a3ffa4fd6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 23 Nov 2014 22:04:09 -0500 Subject: [PATCH] Remove test_vcs directory. --- Makefile.in | 6 ++-- doxygen.config | 1 - internals.pod | 2 +- readme.pod | 1 - test_vcs/.gitignore | 13 -------- test_vcs/Makefile | 76 ------------------------------------------ test_vcs/bench.v | 81 --------------------------------------------- 7 files changed, 3 insertions(+), 177 deletions(-) delete mode 100644 test_vcs/.gitignore delete mode 100644 test_vcs/Makefile delete mode 100644 test_vcs/bench.v diff --git a/Makefile.in b/Makefile.in index 3c9c0ad38..5aee1fe2b 100644 --- a/Makefile.in +++ b/Makefile.in @@ -100,7 +100,7 @@ PACKAGE_VERSION = @PACKAGE_VERSION@ SHELL = /bin/sh -SUBDIRS = src test_verilated test_c test_sc test_sp test_regress test_vcs +SUBDIRS = src test_verilated test_c test_sc test_sp test_regress INFOS = README README.html README.pdf internals.txt internals.html \ internals.pdf verilator.txt verilator.html verilator.1 verilator.pdf @@ -183,7 +183,7 @@ msg_test: all_nomsg .PHONY:test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users -test: test_vcs test_c test_sc test_sp test_verilated test_regress +test: test_c test_sc test_sp test_verilated test_regress else test: test_c test_sc test_sp endif @@ -192,8 +192,6 @@ endif @echo "Type 'make install' to install documentation." @echo -test_vcs: all_nomsg - @(cd test_vcs && $(MAKE)) test_c: all_nomsg @(cd test_c && $(MAKE)) test_c_debug: all_nomsg diff --git a/doxygen.config b/doxygen.config index 8fb007278..bf488bdfd 100644 --- a/doxygen.config +++ b/doxygen.config @@ -637,7 +637,6 @@ INPUT = doxygen-mainpage \ test_sc \ test_sp \ test_v \ - test_vcs \ test_verilated # This tag can be used to specify the character encoding of the source files diff --git a/internals.pod b/internals.pod index 1a458ba55..eba77f395 100644 --- a/internals.pod +++ b/internals.pod @@ -474,7 +474,7 @@ be warning free. =item --enable-longtests In addition to the standard C, SystemC and SystemPerl tests also run the -tests in the C, C and C directories +tests in the C and C directories when using I. This is disabled by default as SystemC/SystemPerl installation problems would otherwise falsely indicate a Verilator problem. diff --git a/readme.pod b/readme.pod index d4340f06c..e6ac8342c 100644 --- a/readme.pod +++ b/readme.pod @@ -199,7 +199,6 @@ The directories in the kit after de-taring are as follows: test_c => Example Verilog->C++ conversion test_sc => Example Verilog->SystemC conversion test_sp => Example Verilog->SystemPerl conversion - test_vcs => Example Verilog->VCS conversion (test the test) test_verilated => Internal tests test_regress => Internal tests diff --git a/test_vcs/.gitignore b/test_vcs/.gitignore deleted file mode 100644 index 485ec449d..000000000 --- a/test_vcs/.gitignore +++ /dev/null @@ -1,13 +0,0 @@ -*.old -*.dmp -*.log -*.csrc -*.vcd -csrc -vcs.key -ucli.key -*.daidir -simv -obj_* -project -INCA_libs diff --git a/test_vcs/Makefile b/test_vcs/Makefile deleted file mode 100644 index 161918383..000000000 --- a/test_vcs/Makefile +++ /dev/null @@ -1,76 +0,0 @@ -#***************************************************************************** -# -# DESCRIPTION: Verilator Example: Makefile for inside source directory -# -# This calls the object directory makefile. That allows the objects to -# be placed in the "current directory" which simplifies the Makefile. -# -# Copyright 2003-2014 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# -#****************************************************************************/ - -default: test - -# This must point to the root of the VERILATOR kit -VERILATOR_ROOT := $(shell pwd)/.. -export VERILATOR_ROOT - -# Pick up PERL and other variable settings -include $(VERILATOR_ROOT)/include/verilated.mk - -###################################################################### - -V_FILES := $(wildcard *.v ../test_v/*.v) - -###################################################################### - -ifneq ($(VCS_HOME),) -test:: vcs -else -test:: novcs -endif - -ifneq ($(NC_ROOT),) -test:: nc -else -test:: nonc -endif - -###################################################################### - -novcs: - @echo "No VCS simulator installed." - @echo "Not running VCS regression test." - -vcs: vcs_passed.log - -simv: $(V_FILES) ../test_v/input.vc - vcs +cli -I -sverilog +define+VCS+1 -f ../test_v/input.vc -q bench.v - -vcs_passed.log : simv - -rm -f test_passed.log - ./simv -l sim.log - grep -q Finished sim.log && grep Finished sim.log > vcs_passed.log - -###################################################################### - -nonc: - @echo "No NC-Verilog simulator installed." - @echo "Not running NC-Verilog regression test." - -nc: nc_passed.log - -nc_passed.log: $(V_FILES) ../test_v/input.vc - ncverilog +define+ncverilog=1 +licqueue -f ../test_v/input.vc -q bench.v - -rm -f nc_passed.log - grep -q Finished ncverilog.log && grep Finished ncverilog.log > nc_passed.log - -###################################################################### - -maintainer-copy:: -clean mostlyclean distclean maintainer-clean:: - -rm -rf obj_dir *.log *.dmp *.vpd simv* *.key csrc INCA_libs - diff --git a/test_vcs/bench.v b/test_vcs/bench.v deleted file mode 100644 index 013901485..000000000 --- a/test_vcs/bench.v +++ /dev/null @@ -1,81 +0,0 @@ -// DESCRIPTION: Verilator Test: Top level testbench for VCS or other fully Verilog compliant simulators -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. - -`timescale 1 ns / 1ns - -module bench; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [39:0] out_quad; // From top of top.v - wire [1:0] out_small; // From top of top.v - wire [69:0] out_wide; // From top of top.v - wire passed; // From top of top.v - // End of automatics - - reg clk; - reg fastclk; - reg reset_l; - reg [1:0] in_small; - reg [39:0] in_quad; - reg [69:0] in_wide; - - // Test cases - top top (/*AUTOINST*/ - // Outputs - .passed (passed), - .out_small (out_small[1:0]), - .out_quad (out_quad[39:0]), - .out_wide (out_wide[69:0]), - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l), - .in_small (in_small[1:0]), - .in_quad (in_quad[39:0]), - .in_wide (in_wide[69:0])); - - //surefire lint_off STMINI - //surefire lint_off STMFVR - //surefire lint_off DLYONE - - integer fh; - - // surefire lint_off CWECBB - initial begin - reset_l = 1'b1; // Want to catch negedge - fastclk = 0; - clk = 0; - forever begin - in_small = 0; - in_wide = 0; - $write("[%0t] %x %x %x %x %x\n", $time, clk, reset_l, passed, out_small, out_wide); - if (($time % 10) == 3) clk = 1'b1; - if (($time % 10) == 8) clk = 1'b0; - if ($time>10) reset_l = 1'b1; - else if ($time > 1) reset_l = 1'b0; - if ($time>60 || passed === 1'b1) begin - if (passed !== 1'b1) begin - $write("A Test failed!!!\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); // Magic if using perl's Log::Detect - fh = $fopen("test_passed.log"); - $fclose(fh); - end - $finish; - end - #1; - fastclk = !fastclk; - end - end - -endmodule - -// Local Variables: -// verilog-library-directories:("." "../test_v") -// compile-command: "vlint --brief -f ../test_v/input.vc bench.v" -// End: