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Merge branch 'master' into develop-v5

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This commit is contained in:
Wilson Snyder 2022-08-31 19:51:07 -04:00
commit 849bb5590a
6 changed files with 130 additions and 105 deletions
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41
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@ -21,22 +21,43 @@ Verilator 5.001 devel
statements) and forks. See docs for details. [Krzysztof Bieganski, Antmicro Ltd]
Verilator 4.225 devel
Verilator 4.227 devel
==========================
**Minor:**
Verilator 4.226 2022-08-31
==========================
**Minor:**
* Add --future0 and --future1 options.
* Support class parameters (#2231) (#3541). [Arkadiusz Kozdra/Antmicro]
* Support wildcard index associative arrays (#3501). [Arkadiusz Kozdra/Antmicro]
* Support negated properties (#3572). [Aleksander Kiryk]
* Support $test$plusargs(expr) (#3489).
* Rename trace rolloverSize() (#3570).
* Improve Verilation speed with --threads on large designs. [Geza Lore]
* Fix struct pattern assignment (#2328) (#3517). [Mostafa Gamal]
* Fix public combo propagation issues (#2905). [Todd Strader]
* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
* Fix incorrect bit op tree optimization (#3470). [algrobman]
* Fix bisonpre for MSYS2 (#3471).
* Fix max memory usage (#3483). [Kamil Rakoczy]
* Fix empty string arguments to display (#3484). [Grulfen]
* Fix table misoptimizing away display (#3488). [Stefan Post]
* Fix unique_ptr memory header for MinGW64 (#3493).
* Fix $dump systemtask with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta]
* Fix wrong bit op tree optimization (#3509). [Nathan Graybeal]
* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
* Fix nested default assignment for struct pattern (#3511) (#3524). [Mostafa Gamal]
* Fix sformat string incorrectly cleared (#3515) (#3519). [Gustav Svensk]
* Fix segfault exporting non-existant package (#3535).
* Fix void-cast queue pop_front or pop_back (#3542) (#3364). [Drew Ranck]
* Fix case statement comparing string literal (#3544). [Gustav Svensk]
* Fix --hierarchical with order-based pin connections (#3583). [Kelin9298]
* Improve Verilation speed with --threads on large designs. [Geza Lore]
* Rename trace rolloverSize() (#3570).
* Fix === with some tristate constants (#3551). [Ryszard Rozak]
* Fix converting subclasses to string (#3552). [Arkadiusz Kozdra/Antmicro]
* Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298]
Verilator 4.224 2022-06-19
@ -57,7 +78,7 @@ Verilator 4.224 2022-06-19
* Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD]
* Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
* Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
* Internal prep work towards timing control. [Krzysztof Bieganski]
* Internal prep work towards timing control. [Krzysztof Bieganski/Antmicro]
* Fix hang with large case statement optimization (#3405). [Mike Urbach]
* Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy]
* Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu]
@ -224,7 +245,7 @@ Verilator 4.212 2021-09-01
* Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore]
* Support unpacked array localparams in tasks/functions (#3078). [Geza Lore]
* Support timeunit/timeprecision in $unit.
* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski]
* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski/Antmicro]
* Add --instr-count-dpi to tune assumed DPI import cost for multithreaded
model scheduling. Default value changed to 200 (#3068). [Yinan Xu]
* Output files are split based on the set of headers required
@ -289,7 +310,7 @@ Verilator 4.204 2021-06-12
* Prep work towards better ccache hashing/performance. [Geza Lore]
* Fix assertion failure in bitOpTree optimization (#2891) (#2899). [Raynard Qiao]
* Fix DPI functions not seen as vpiModule (#2893). [Todd Strader]
* Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski]
* Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski/Antmicro]
* Fix slowdown in elaboration (#2911). [Nathan Graybeal]
* Fix initialization of assoc in assoc array (#2914). [myftptoyman]
* Fix make support for gmake 3.x (#2920) (#2921). [Philipp Wagner]
@ -404,7 +425,7 @@ Verilator 4.108 2021-01-10
**Major:**
* Many VPI changes for IEEE compatibility, which may alter behavior from previous releases.
* Support randomize() class method and rand (#2607). [Krzysztof Bieganski]
* Support randomize() class method and rand (#2607). [Krzysztof Bieganski/Antmicro]
**Minor:**
@ -464,7 +485,7 @@ Verilator 4.104 2020-11-14
* Support queue and associative array 'with' statements (#2616).
* Support queue slicing (#2326).
* Support associative array pattern assignments and defaults.
* Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski]
* Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski/Antmicro]
* Add error on typedef referencing self (#2539). [Cody Piersall]
* With --debug, turn off address space layout randomization.
* Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett]

4
src/V3LinkDot.cpp
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@ -1500,6 +1500,10 @@ private:
refp, nullptr /*classOrPackagep*/);
symp->exported(false);
refp->pinNum(nodep->pinNum());
// Put the variable where the port is, so that variables stay
// in pin number sorted order. Otherwise hierarchical or XML
// may botch by-position instances.
nodep->addHereThisAsNext(refp->unlinkFrBack());
}
// Ports not needed any more
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);

10
test_regress/t/t_hier_bynum.v
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@ -3,11 +3,11 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2022 by Wilson Snyder.
module flop (
output reg q,
input wire d,
input wire clk
);
module flop (q, d, clk);
// No AUTOARG; order of below is different from port order above
input wire clk;
output reg q;
input wire d;
// verilator hier_block

6
test_regress/t/t_udp_bad.out
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@ -9,10 +9,10 @@
%Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1'
10 | udp_x x (a, b);
| ^
%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules
15 | tri a_bad;
| ^~~~~
%Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules
17 | output c_bad;
| ^~~~~
%Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules
15 | tri a_bad;
| ^~~~~
%Error: Exiting due to

50
test_regress/t/t_xml_first.out
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@ -18,67 +18,67 @@
</cells>
<netlist>
<module loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d"/>
<var loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q"/>
<var loc="d,17,22,17,29" name="between" dtype_id="2" vartype="logic" origName="between"/>
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d"/>
<var loc="d,17,22,17,29" name="between" dtype_id="1" vartype="logic" origName="between"/>
<instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
<varref loc="d,20,14,20,21" name="between" dtype_id="2"/>
<varref loc="d,20,14,20,21" name="between" dtype_id="1"/>
</port>
<port loc="d,21,12,21,15" name="clk" direction="in" portIndex="2">
<varref loc="d,21,42,21,45" name="clk" dtype_id="1"/>
<varref loc="d,21,42,21,45" name="clk" dtype_id="2"/>
</port>
<port loc="d,22,12,22,13" name="d" direction="in" portIndex="3">
<varref loc="d,22,42,22,43" name="d" dtype_id="2"/>
<varref loc="d,22,42,22,43" name="d" dtype_id="1"/>
</port>
</instance>
<instance loc="d,25,6,25,11" name="cell2" defName="mod2" origName="cell2">
<port loc="d,25,14,25,15" name="d" direction="in" portIndex="1">
<varref loc="d,25,16,25,23" name="between" dtype_id="2"/>
<varref loc="d,25,16,25,23" name="between" dtype_id="1"/>
</port>
<port loc="d,26,14,26,15" name="q" direction="out" portIndex="2">
<varref loc="d,26,42,26,43" name="q" dtype_id="2"/>
<varref loc="d,26,42,26,43" name="q" dtype_id="1"/>
</port>
<port loc="d,27,14,27,17" name="clk" direction="in" portIndex="3">
<varref loc="d,27,42,27,45" name="clk" dtype_id="1"/>
<varref loc="d,27,42,27,45" name="clk" dtype_id="2"/>
</port>
</instance>
</module>
<module loc="d,46,8,46,12" name="mod2" origName="mod2">
<var loc="d,48,10,48,13" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign loc="d,53,13,53,14" dtype_id="2">
<varref loc="d,53,15,53,16" name="d" dtype_id="2"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="2"/>
<var loc="d,48,10,48,13" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,53,15,53,16" name="d" dtype_id="1"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="1"/>
</contassign>
</module>
<module loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
<var loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var loc="d,34,24,34,27" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var loc="d,34,24,34,27" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="1"/>
<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
</senitem>
</sentree>
<assigndly loc="d,42,8,42,10" dtype_id="2">
<varref loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref loc="d,42,6,42,7" name="q" dtype_id="2"/>
<assigndly loc="d,42,8,42,10" dtype_id="1">
<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
<varref loc="d,42,6,42,7" name="q" dtype_id="1"/>
</assigndly>
</always>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,34,24,34,27" id="1" name="logic"/>
<basicdtype loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>

124
test_regress/t/t_xml_flat.out
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@ -15,99 +15,99 @@
</cells>
<netlist>
<module loc="d,7,8,7,9" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="t.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="t.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,15,22,15,23" name="t.q" dtype_id="2" vartype="logic" origName="q"/>
<var loc="d,17,22,17,29" name="t.between" dtype_id="2" vartype="logic" origName="between"/>
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,15,22,15,23" name="t.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,13,10,13,13" name="t.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="t.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,17,22,17,29" name="t.between" dtype_id="1" vartype="logic" origName="between"/>
<var loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2" vartype="logic" origName="q"/>
<var loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<var loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2" vartype="logic" origName="q"/>
<var loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1" vartype="logic" origName="q"/>
<topscope loc="d,7,8,7,9">
<scope loc="d,7,8,7,9" name="TOP">
<varscope loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varscope loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="1"/>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="2"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="2"/>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="2"/>
<varscope loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varscope loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="1"/>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="2"/>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="2"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="1"/>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="2"/>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="2"/>
<assignalias loc="d,13,10,13,13" dtype_id="1">
<varref loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varref loc="d,13,10,13,13" name="clk" dtype_id="1"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
<assignalias loc="d,15,22,15,23" dtype_id="1">
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
</assignalias>
<assignalias loc="d,14,16,14,17" dtype_id="2">
<varref loc="d,14,16,14,17" name="d" dtype_id="2"/>
<varref loc="d,14,16,14,17" name="d" dtype_id="2"/>
<assignalias loc="d,13,10,13,13" dtype_id="2">
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,15,22,15,23" dtype_id="2">
<varref loc="d,15,22,15,23" name="q" dtype_id="2"/>
<varref loc="d,15,22,15,23" name="q" dtype_id="2"/>
<assignalias loc="d,14,16,14,17" dtype_id="1">
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,34,24,34,27" dtype_id="1">
<varref loc="d,34,24,34,27" name="t.clk" dtype_id="1"/>
<varref loc="d,34,24,34,27" name="cell1.clk" dtype_id="1"/>
<assignalias loc="d,34,24,34,27" dtype_id="2">
<varref loc="d,34,24,34,27" name="t.clk" dtype_id="2"/>
<varref loc="d,34,24,34,27" name="cell1.clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,35,30,35,31" dtype_id="2">
<varref loc="d,35,30,35,31" name="t.d" dtype_id="2"/>
<varref loc="d,35,30,35,31" name="cell1.d" dtype_id="2"/>
<assignalias loc="d,35,30,35,31" dtype_id="1">
<varref loc="d,35,30,35,31" name="t.d" dtype_id="1"/>
<varref loc="d,35,30,35,31" name="cell1.d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,36,30,36,31" dtype_id="2">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="2"/>
<varref loc="d,36,30,36,31" name="cell1.q" dtype_id="2"/>
<assignalias loc="d,36,30,36,31" dtype_id="1">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
<varref loc="d,36,30,36,31" name="cell1.q" dtype_id="1"/>
</assignalias>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="1"/>
<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
</senitem>
</sentree>
<assigndly loc="d,42,8,42,10" dtype_id="2">
<varref loc="d,42,11,42,12" name="d" dtype_id="2"/>
<varref loc="d,42,6,42,7" name="t.between" dtype_id="2"/>
<assigndly loc="d,42,8,42,10" dtype_id="1">
<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
<varref loc="d,42,6,42,7" name="t.between" dtype_id="1"/>
</assigndly>
</always>
<assignalias loc="d,48,10,48,13" dtype_id="1">
<varref loc="d,48,10,48,13" name="t.clk" dtype_id="1"/>
<varref loc="d,48,10,48,13" name="cell2.clk" dtype_id="1"/>
<assignalias loc="d,48,10,48,13" dtype_id="2">
<varref loc="d,48,10,48,13" name="t.clk" dtype_id="2"/>
<varref loc="d,48,10,48,13" name="cell2.clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,49,16,49,17" dtype_id="2">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="2"/>
<varref loc="d,49,16,49,17" name="cell2.d" dtype_id="2"/>
<assignalias loc="d,49,16,49,17" dtype_id="1">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
<varref loc="d,49,16,49,17" name="cell2.d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,50,22,50,23" dtype_id="2">
<varref loc="d,50,22,50,23" name="t.q" dtype_id="2"/>
<varref loc="d,50,22,50,23" name="cell2.q" dtype_id="2"/>
<assignalias loc="d,50,22,50,23" dtype_id="1">
<varref loc="d,50,22,50,23" name="t.q" dtype_id="1"/>
<varref loc="d,50,22,50,23" name="cell2.q" dtype_id="1"/>
</assignalias>
<contassign loc="d,53,13,53,14" dtype_id="2">
<varref loc="d,53,15,53,16" name="t.between" dtype_id="2"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="2"/>
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,53,15,53,16" name="t.between" dtype_id="1"/>
<varref loc="d,53,11,53,12" name="q" dtype_id="1"/>
</contassign>
</scope>
</topscope>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,34,24,34,27" id="1" name="logic"/>
<basicdtype loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>