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Update default --mod-prefix when --prefix is repeated

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Fixes #3603
This commit is contained in:
Geza Lore 2022-09-12 17:21:27 +01:00
parent 4d49db48a3
commit 08b6bdddf9
3 changed files with 85 additions and 4 deletions
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5
src/V3Options.cpp
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@ -1270,10 +1270,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
DECL_OPTION("-pins-uint8", OnOff, &m_pinsUint8);
DECL_OPTION("-pipe-filter", Set, &m_pipeFilter);
DECL_OPTION("-pp-comments", OnOff, &m_ppComments);
DECL_OPTION("-prefix", CbVal, [this](const char* valp) {
m_prefix = valp;
if (m_modPrefix == "") m_modPrefix = m_prefix;
});
DECL_OPTION("-prefix", Set, &m_prefix);
DECL_OPTION("-private", CbCall, [this]() { m_public = false; });
DECL_OPTION("-prof-c", OnOff, &m_profC);
DECL_OPTION("-prof-cfuncs", CbCall, [this]() { m_profC = m_profCFuncs = true; });

49
test_regress/t/t_flag_prefix.pl Executable file
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@ -0,0 +1,49 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Geza Lore. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ["--prefix t_flag_prefix", # should be overridden
"--prefix Vprefix",
"--exe", "--main", "--stats", "--build"],
verilator_make_cmake => 0,
verilator_make_gmake => 0,
make_main => 0,
);
execute(
check_finished => 1,
executable => "$Self->{obj_dir}/Vprefix",
);
sub check_files {
foreach my $path (glob("$Self->{obj_dir}/*")) {
my $filename = substr $path, ((length $Self->{obj_dir}) + 1);
next if ($filename =~ /^.*\.log$/);
if ($filename =~ /t_flag_prefix/) {
error("bad filename $filename");
next;
}
next if ($filename =~ /^(.*\.(o|a)|Vprefix)$/);
my $fh = IO::File->new("<$path") or error("$! $filenme");
while (defined(my $line = $fh->getline)) {
$line =~ s/--prefix V?t_flag_prefix//g;
$line =~ s/obj_vlt\/t_flag_prefix//g;
$line =~ s/t\/t_flag_prefix\.v//g;
error("bad line in $filename: $line") if $line =~ /t_flag_prefix/;
}
}
}
check_files();
ok(1);
1;

35
test_regress/t/t_flag_prefix.v Executable file
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@ -0,0 +1,35 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module t;
sub sub();
endmodule
module sub;
// no_inline_module, so it goes into separate file
/* verilator no_inline_module */
// Goes into const pool which is separate file
wire bit [255:0] C = {32'h1111_1111,
32'h2222_2222,
32'h3333_3333,
32'h4444_4444,
32'h5555_5555,
32'h6666_6666,
32'h7777_7777,
32'h8888_8888};
initial begin
// Note: Base index via $c to prevent optimization
$display("0x%32x", C[$c(0*32)+:32]);
$display("0x%32x", C[$c(2*32)+:32]);
$display("0x%32x", C[$c(4*32)+:32]);
$display("0x%32x", C[$c(6*32)+:32]);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule