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Parser hack

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Todd Strader 2020-03-01 19:25:56 -05:00
parent 8535fad052
commit 6727a41d7f
1 changed files with 2 additions and 0 deletions
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src/verilog.y
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@ -3695,7 +3695,9 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
| ~l~expr '*' ~r~expr { $$ = new AstMul ($2,$1,$3); }
| ~l~expr '/' ~r~expr { $$ = new AstDiv ($2,$1,$3); }
| ~l~expr '%' ~r~expr { $$ = new AstModDiv ($2,$1,$3); }
| type_reference yP_EQUAL type_reference { $$ = new AstEq ($2,$1,$3); }
| ~l~expr yP_EQUAL ~r~expr { $$ = new AstEq ($2,$1,$3); }
| type_reference yP_NOTEQUAL type_reference { $$ = new AstNeq ($2,$1,$3); }
| ~l~expr yP_NOTEQUAL ~r~expr { $$ = new AstNeq ($2,$1,$3); }
| ~l~expr yP_CASEEQUAL ~r~expr { $$ = new AstEqCase ($2,$1,$3); }
| ~l~expr yP_CASENOTEQUAL ~r~expr { $$ = new AstNeqCase ($2,$1,$3); }