From 6727a41d7f175323b7c155c0f6d7d78d10f4fab8 Mon Sep 17 00:00:00 2001
From: Todd Strader <todd.strader@gmail.com>
Date: Sun, 1 Mar 2020 19:25:56 -0500
Subject: [PATCH] Parser hack

---
 src/verilog.y | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/verilog.y b/src/verilog.y
index c7ba7f6b0..878f0c9b6 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3695,7 +3695,9 @@ expr<nodep>:			// IEEE: part of expression/constant_expression/primary
 	|	~l~expr '*' ~r~expr			{ $$ = new AstMul	($2,$1,$3); }
 	|	~l~expr '/' ~r~expr			{ $$ = new AstDiv	($2,$1,$3); }
 	|	~l~expr '%' ~r~expr			{ $$ = new AstModDiv	($2,$1,$3); }
+	|	type_reference yP_EQUAL type_reference	{ $$ = new AstEq	($2,$1,$3); }
 	|	~l~expr yP_EQUAL ~r~expr		{ $$ = new AstEq	($2,$1,$3); }
+	|	type_reference yP_NOTEQUAL type_reference { $$ = new AstNeq	($2,$1,$3); }
 	|	~l~expr yP_NOTEQUAL ~r~expr		{ $$ = new AstNeq	($2,$1,$3); }
 	|	~l~expr yP_CASEEQUAL ~r~expr		{ $$ = new AstEqCase	($2,$1,$3); }
 	|	~l~expr yP_CASENOTEQUAL ~r~expr		{ $$ = new AstNeqCase	($2,$1,$3); }