forked from github/verilator
Support assert property statement-else-statement
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81e8388c3f
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@ -182,7 +182,7 @@ private:
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const bool force = VN_IS(nodep, AssertIntrinsic);
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if (passsp) passsp = newIfAssertOn(passsp, force);
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if (failsp) failsp = newIfAssertOn(failsp, force);
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if (!failsp) failsp = newFireAssertUnchecked(nodep, "'assert' failed.");
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if (!passsp && !failsp) failsp = newFireAssertUnchecked(nodep, "'assert' failed.");
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ifp = new AstIf{nodep->fileline(), propp, passsp, failsp};
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ifp->isBoundsCheck(true); // To avoid LATCH warning
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// It's more LIKELY that we'll take the nullptr if clause
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@ -5772,14 +5772,13 @@ concurrent_assertion_item<nodep>: // IEEE: concurrent_assertion_item
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concurrent_assertion_statement<nodep>: // ==IEEE: concurrent_assertion_statement
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// // IEEE: assert_property_statement
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// // IEEE: assume_property_statement
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//UNSUP remove below:
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assertOrAssume yPROPERTY '(' property_spec ')' elseStmtBlock
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{ $$ = new AstAssert{$1, new AstSampled{$1, $4}, nullptr, $6, false}; }
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//UNSUP remove above:
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// // action_block expanded here
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//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' stmt %prec prLOWER_THAN_ELSE {}
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//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' stmt yELSE stmt {}
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//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' yELSE stmt {}
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assertOrAssume yPROPERTY '(' property_spec ')' stmt %prec prLOWER_THAN_ELSE
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{ $$ = new AstAssert{$1, new AstSampled{$1, $4}, $6, nullptr, false}; }
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| assertOrAssume yPROPERTY '(' property_spec ')' stmt yELSE stmt
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{ $$ = new AstAssert{$1, new AstSampled{$1, $4}, $6, $8, false}; }
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| assertOrAssume yPROPERTY '(' property_spec ')' yELSE stmt
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{ $$ = new AstAssert{$1, new AstSampled{$1, $4}, nullptr, $7, false}; }
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// // IEEE: cover_property_statement
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| yCOVER yPROPERTY '(' property_spec ')' stmtBlock
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{ $$ = new AstCover{$1, $4, $6, false}; }
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@ -5797,11 +5796,6 @@ concurrent_assertion_statement<nodep>: // ==IEEE: concurrent_assertion_statemen
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{ $$ = new AstRestrict{$1, $4}; }
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;
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elseStmtBlock<nodep>: // Part of concurrent_assertion_statement
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';' { $$ = nullptr; }
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| yELSE stmtBlock { $$ = $2; }
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;
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property_declaration<nodeFTaskp>: // ==IEEE: property_declaration
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property_declarationFront property_port_listE ';' property_declarationBody
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yENDPROPERTY endLabelE
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@ -4,6 +4,8 @@
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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@ -14,6 +16,7 @@ module t (/*AUTOARG*/
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Test1 t1(clk, a, b);
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Test2 t2(clk, a, b);
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Test3 t3(clk, a, b);
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initial begin
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a = 0;
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@ -54,3 +57,33 @@ module Test2(
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assert property (@(posedge clk) a == b);
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endmodule
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module Test3(
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clk, a, b
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);
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input clk;
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input [3:0] a, b;
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int hits[10];
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assert property (@(posedge clk) a == b) hits[1]=1;
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assert property (@(posedge clk) a == b) else hits[2]=1;
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assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1;
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assert property (@(posedge clk) a != b) hits[5]=1;
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assert property (@(posedge clk) a != b) else hits[6]=1;
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assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1;
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final begin
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`checkd(hits[1], 1);
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`checkd(hits[2], 0);
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`checkd(hits[3], 1);
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`checkd(hits[4], 0);
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`checkd(hits[5], 0);
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`checkd(hits[6], 1);
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`checkd(hits[7], 0);
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`checkd(hits[8], 1);
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end
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endmodule
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