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Parse 'expect', still unsupported.

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This commit is contained in:
Wilson Snyder 2023-03-10 21:48:56 -05:00
parent 4532680e5f
commit 81e8388c3f
5 changed files with 97 additions and 10 deletions
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2
src/verilog.l
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@ -525,7 +525,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"endproperty" { FL; return yENDPROPERTY; }
"endsequence" { FL; return yENDSEQUENCE; }
"enum" { FL; return yENUM; }
"expect" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"expect" { FL; return yEXPECT; }
"export" { FL; return yEXPORT; }
"extends" { FL; return yEXTENDS; }
"extern" { FL; return yEXTERN; }

28
src/verilog.y
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@ -607,7 +607,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yENUM "enum"
%token<fl> yEVENT "event"
%token<fl> yEVENTUALLY "eventually"
//UNSUP %token<fl> yEXPECT "expect"
%token<fl> yEXPECT "expect"
%token<fl> yEXPORT "export"
%token<fl> yEXTENDS "extends"
%token<fl> yEXTERN "extern"
@ -3603,7 +3603,10 @@ statement_item<nodep>: // IEEE: statement_item
// // IEEE: wait_statement
| yWAIT '(' expr ')' stmtBlock { $$ = new AstWait{$1, $3, $5}; }
| yWAIT yFORK ';' { $$ = new AstWaitFork{$1}; }
//UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' action_block { UNSUP }
// // action_block expanded here
//UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' stmt %prec prLOWER_THAN_ELSE { UNSUP }
//UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' stmt yELSE stmt { UNSUP }
//UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' yELSE stmt { UNSUP }
//
// // IEEE: procedural_assertion_statement
| procedural_assertion_statement { $$ = $1; }
@ -3613,7 +3616,14 @@ statement_item<nodep>: // IEEE: statement_item
// // IEEE: randcase_statement
| yRANDCASE rand_case_itemList yENDCASE { $$ = new AstRandCase{$1, $2}; }
//
//UNSUP expect_property_statement { $$ = $1; }
// // IEEE: expect_property_statement
// // action_block expanded here
| yEXPECT '(' property_spec ')' stmt %prec prLOWER_THAN_ELSE
{ $$ = nullptr; BBUNSUP($1, "Unsupported: expect"); }
| yEXPECT '(' property_spec ')' stmt yELSE stmt
{ $$ = nullptr; BBUNSUP($1, "Unsupported: expect"); }
| yEXPECT '(' property_spec ')' yELSE stmt
{ $$ = nullptr; BBUNSUP($1, "Unsupported: expect"); }
//
| error ';' { $$ = nullptr; }
;
@ -5716,7 +5726,7 @@ immediate_assertion_statement<nodep>: // ==IEEE: immediate_assertion_statement
;
simple_immediate_assertion_statement<nodep>: // ==IEEE: simple_immediate_assertion_statement
// // action_block expanded here, for compatibility with AstAssert
// // action_block expanded here, for compatibility with AstAssert
assertOrAssume '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
{ $$ = new AstAssert{$1, $3, $5, nullptr, true}; }
| assertOrAssume '(' expr ')' yELSE stmtBlock
@ -5751,10 +5761,6 @@ deferred_immediate_assertion_statement<nodep>: // ==IEEE: deferred_immediate_as
| yCOVER final_zero '(' expr ')' stmt { $$ = new AstCover{$1, $4, $6, true}; }
;
//UNSUPexpect_property_statement<nodep>: // ==IEEE: expect_property_statement
//UNSUP yEXPECT '(' property_spec ')' action_block { }
//UNSUP ;
concurrent_assertion_item<nodep>: // IEEE: concurrent_assertion_item
concurrent_assertion_statement { $$ = $1; }
| id/*block_identifier*/ ':' concurrent_assertion_statement
@ -5769,7 +5775,11 @@ concurrent_assertion_statement<nodep>: // ==IEEE: concurrent_assertion_statemen
//UNSUP remove below:
assertOrAssume yPROPERTY '(' property_spec ')' elseStmtBlock
{ $$ = new AstAssert{$1, new AstSampled{$1, $4}, nullptr, $6, false}; }
//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' action_block { }
//UNSUP remove above:
// // action_block expanded here
//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' stmt %prec prLOWER_THAN_ELSE {}
//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' stmt yELSE stmt {}
//UNSUP assertOrAssume yPROPERTY '(' property_spec ')' yELSE stmt {}
// // IEEE: cover_property_statement
| yCOVER yPROPERTY '(' property_spec ')' stmtBlock
{ $$ = new AstCover{$1, $4, $6, false}; }

29
test_regress/t/t_expect.out Normal file
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@ -0,0 +1,29 @@
%Error-UNSUPPORTED: t/t_expect.v:19:32: Unsupported: ## () cycle delay range expression
19 | expect (@(posedge clk) a ##1 b) a = 110;
| ^~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_expect.v:19:34: Unsupported: ## (in sequence expression)
19 | expect (@(posedge clk) a ##1 b) a = 110;
| ^
%Error-UNSUPPORTED: t/t_expect.v:19:7: Unsupported: expect
19 | expect (@(posedge clk) a ##1 b) a = 110;
| ^~~~~~
%Error-UNSUPPORTED: t/t_expect.v:21:32: Unsupported: ## () cycle delay range expression
21 | expect (@(posedge clk) a ##1 b) else a = 299;
| ^~
%Error-UNSUPPORTED: t/t_expect.v:21:34: Unsupported: ## (in sequence expression)
21 | expect (@(posedge clk) a ##1 b) else a = 299;
| ^
%Error-UNSUPPORTED: t/t_expect.v:21:7: Unsupported: expect
21 | expect (@(posedge clk) a ##1 b) else a = 299;
| ^~~~~~
%Error-UNSUPPORTED: t/t_expect.v:23:32: Unsupported: ## () cycle delay range expression
23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399;
| ^~
%Error-UNSUPPORTED: t/t_expect.v:23:34: Unsupported: ## (in sequence expression)
23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399;
| ^
%Error-UNSUPPORTED: t/t_expect.v:23:7: Unsupported: expect
23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399;
| ^~~~~~
%Error: Exiting due to

20
test_regress/t/t_expect.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert --timing'],
fails => 1,
);
ok(1);
1;

28
test_regress/t/t_expect.v Normal file
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@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg a;
reg b;
initial begin
#10;
expect (@(posedge clk) a ##1 b) a = 110;
#10;
expect (@(posedge clk) a ##1 b) else a = 299;
#10;
expect (@(posedge clk) a ##1 b) a = 300; else a = 399;
end
// TODO set a/b appropriately - this is just a parsing test currently
endmodule