forked from github/verilator
Fix shift with XOR mis-optimization, bug776.
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@ -9,7 +9,7 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Support SV 2012 package import before port list.
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**** Fix shift corner issues, bug765, bug766, bug768, bug772. [Clifford Wolf]
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**** Fix shift corner-cases, bug765, bug766, bug768, bug772, bug776. [Clifford Wolf]
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**** Fix C compiler interpreting signing, bug773. [Clifford Wolf]
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@ -2070,7 +2070,7 @@ private:
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TREEOP ("AstAnd {operandShiftSame(nodep)}", "replaceShiftSame(nodep)");
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TREEOP ("AstOr {operandShiftSame(nodep)}", "replaceShiftSame(nodep)");
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TREEOP ("AstXor {operandShiftSame(nodep)}", "replaceShiftSame(nodep)");
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TREEOP ("AstXnor{operandShiftSame(nodep)}", "replaceShiftSame(nodep)");
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// "AstXnor{operandShiftSame(nodep)}", // Cannot ShiftSame as the shifted-in zeros might create a one
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// Note can't simplify a extend{extends}, extends{extend}, as the sign bits end up in the wrong places
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TREEOPV("AstExtend {$lhsp.castExtend}", "replaceExtend(nodep, nodep->lhsp()->castExtend()->lhsp())");
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TREEOPV("AstExtendS{$lhsp.castExtendS}", "replaceExtend(nodep, nodep->lhsp()->castExtendS()->lhsp())");
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@ -20,6 +20,7 @@
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reg [2:0] w3_u;
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reg [3:0] w4_u;
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reg [4:0] w5_u;
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reg [5:0] w6_u;
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reg [15:0] w16a_u;
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reg [15:0] w16_u;
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real r;
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@ -147,6 +148,11 @@
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w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u);
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`checkh(w5_s, 5'b0);
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//bug776
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w4_u = `c(4, 1);
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w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u);
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`checkh(w4_u, 4'b1111);
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if (fail) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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