From 5f8f474c0ceb460c473c473f2e0ac0bbf26dc487 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 26 May 2014 18:16:52 -0400
Subject: [PATCH] Fix shift with XOR mis-optimization, bug776.

---
 Changes                         | 2 +-
 src/V3Const.cpp                 | 2 +-
 test_regress/t/t_math_signed5.v | 6 ++++++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Changes b/Changes
index 8256ec084..96b3cce30 100644
--- a/Changes
+++ b/Changes
@@ -9,7 +9,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Support SV 2012 package import before port list.
 
-****  Fix shift corner issues, bug765, bug766, bug768, bug772. [Clifford Wolf]
+****  Fix shift corner-cases, bug765, bug766, bug768, bug772, bug776. [Clifford Wolf]
 
 ****  Fix C compiler interpreting signing, bug773. [Clifford Wolf]
 
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index f7bdffc5a..73d5aaeef 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2070,7 +2070,7 @@ private:
     TREEOP ("AstAnd {operandShiftSame(nodep)}",		"replaceShiftSame(nodep)");
     TREEOP ("AstOr  {operandShiftSame(nodep)}",		"replaceShiftSame(nodep)");
     TREEOP ("AstXor {operandShiftSame(nodep)}",		"replaceShiftSame(nodep)");
-    TREEOP ("AstXnor{operandShiftSame(nodep)}",		"replaceShiftSame(nodep)");
+    //      "AstXnor{operandShiftSame(nodep)}",		// Cannot ShiftSame as the shifted-in zeros might create a one
     // Note can't simplify a extend{extends}, extends{extend}, as the sign bits end up in the wrong places
     TREEOPV("AstExtend {$lhsp.castExtend}",		"replaceExtend(nodep, nodep->lhsp()->castExtend()->lhsp())");
     TREEOPV("AstExtendS{$lhsp.castExtendS}",		"replaceExtend(nodep, nodep->lhsp()->castExtendS()->lhsp())");
diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v
index c45e92bfd..72e4f95ad 100644
--- a/test_regress/t/t_math_signed5.v
+++ b/test_regress/t/t_math_signed5.v
@@ -20,6 +20,7 @@
    reg [2:0] 	    w3_u;
    reg [3:0] 	    w4_u;
    reg [4:0] 	    w5_u;
+   reg [5:0] 	    w6_u;
    reg [15:0] 	    w16a_u;
    reg [15:0] 	    w16_u;
    real 	    r;
@@ -147,6 +148,11 @@
       w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u);
       `checkh(w5_s, 5'b0);
 
+      //bug776
+      w4_u = `c(4, 1);
+      w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u);
+      `checkh(w4_u, 4'b1111);
+
       if (fail) $stop;
       $write("*-* All Finished *-*\n");
       $finish;