forked from github/verilator
Fix interface inside generate, bug998.
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2
Changes
@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix constant function assigned to packed structs, bug997. [Johan Bjork]
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**** Fix interface inside generate, bug998. [Johan Bjork]
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**** Fix $signed casts under generates, bug999. [Clifford Wolf]
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@ -56,7 +56,7 @@ public:
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m_anyFuncInBegin = false;
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}
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~BeginState() {}
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void userMarkChanged(AstNodeFTask* nodep) {
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void userMarkChanged(AstNode* nodep) {
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nodep->user1(true);
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m_anyFuncInBegin = true;
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}
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@ -166,6 +166,7 @@ private:
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if (m_unnamedScope != "") {
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// Rename it
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nodep->name(m_unnamedScope+"__DOT__"+nodep->name());
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m_statep->userMarkChanged(nodep);
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// Move to module
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nodep->unlinkFrBack();
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if (m_ftaskp) m_ftaskp->addStmtsp(nodep); // Begins under funcs just move into the func
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@ -175,6 +176,7 @@ private:
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virtual void visit(AstCell* nodep, AstNUser*) {
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UINFO(8," CELL "<<nodep<<endl);
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if (m_namedScope != "") {
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m_statep->userMarkChanged(nodep);
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// Rename it
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nodep->name(m_namedScope+"__DOT__"+nodep->name());
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UINFO(8," rename to "<<nodep->name()<<endl);
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@ -182,6 +184,7 @@ private:
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nodep->unlinkFrBack();
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m_modp->addStmtp(nodep);
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstScopeName* nodep, AstNUser*) {
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// If there's a %m in the display text, we add a special node that will contain the name()
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@ -249,6 +252,21 @@ private:
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstVarRef* nodep, AstNUser*) {
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if (nodep->varp()->user1()) { // It was converted
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UINFO(9, " relinVarRef "<<nodep<<endl);
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nodep->name(nodep->varp()->name());
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstIfaceRefDType* nodep, AstNUser*) {
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// May have changed cell names
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// TypeTable is always after all modules, so names are stable
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UINFO(8," IFACEREFDTYPE "<<nodep<<endl);
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if (nodep->cellp()) nodep->cellName(nodep->cellp()->name());
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UINFO(8," rename to "<<nodep<<endl);
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nodep->iterateChildren(*this);
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}
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//--------------------
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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18
test_regress/t/t_interface_gen5.pl
Executable file
18
test_regress/t/t_interface_gen5.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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31
test_regress/t/t_interface_gen5.v
Normal file
31
test_regress/t/t_interface_gen5.v
Normal file
@ -0,0 +1,31 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// bug998
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interface intf
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#(parameter PARAM = 0)
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();
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logic val;
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endinterface
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module t1(intf mod_intf);
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initial begin
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$display("%d", mod_intf.val);
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end
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endmodule
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module t();
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generate
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begin : TestIf
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intf #(.PARAM(1)) my_intf;
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t1 t (.mod_intf(my_intf));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endgenerate
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endmodule
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