From 52ae451f5c570ae5fad3c6f7db500749d25596cc Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 14 Nov 2015 09:06:09 -0500
Subject: [PATCH] Fix interface inside generate, bug998.

---
 Changes                            |  2 ++
 src/V3Begin.cpp                    | 20 ++++++++++++++++++-
 test_regress/t/t_interface_gen5.pl | 18 +++++++++++++++++
 test_regress/t/t_interface_gen5.v  | 31 ++++++++++++++++++++++++++++++
 4 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_interface_gen5.pl
 create mode 100644 test_regress/t/t_interface_gen5.v

diff --git a/Changes b/Changes
index 6cc11b0c7..8e139e7eb 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix constant function assigned to packed structs, bug997. [Johan Bjork]
 
+****  Fix interface inside generate, bug998. [Johan Bjork]
+
 ****  Fix $signed casts under generates, bug999. [Clifford Wolf]
 
 
diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index d56467369..766f1f4ad 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -56,7 +56,7 @@ public:
 	m_anyFuncInBegin = false;
     }
     ~BeginState() {}
-    void userMarkChanged(AstNodeFTask* nodep) {
+    void userMarkChanged(AstNode* nodep) {
 	nodep->user1(true);
 	m_anyFuncInBegin = true;
     }
@@ -166,6 +166,7 @@ private:
 	if (m_unnamedScope != "") {
 	    // Rename it
 	    nodep->name(m_unnamedScope+"__DOT__"+nodep->name());
+	    m_statep->userMarkChanged(nodep);
 	    // Move to module
 	    nodep->unlinkFrBack();
 	    if (m_ftaskp) m_ftaskp->addStmtsp(nodep);   // Begins under funcs just move into the func
@@ -175,6 +176,7 @@ private:
     virtual void visit(AstCell* nodep, AstNUser*) {
 	UINFO(8,"   CELL "<<nodep<<endl);
 	if (m_namedScope != "") {
+	    m_statep->userMarkChanged(nodep);
 	    // Rename it
 	    nodep->name(m_namedScope+"__DOT__"+nodep->name());
 	    UINFO(8,"     rename to "<<nodep->name()<<endl);
@@ -182,6 +184,7 @@ private:
 	    nodep->unlinkFrBack();
 	    m_modp->addStmtp(nodep);
 	}
+	nodep->iterateChildren(*this);
     }
     virtual void visit(AstScopeName* nodep, AstNUser*) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
@@ -249,6 +252,21 @@ private:
 	}
 	nodep->iterateChildren(*this);
     }
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (nodep->varp()->user1()) { // It was converted
+	    UINFO(9, "    relinVarRef "<<nodep<<endl);
+	    nodep->name(nodep->varp()->name());
+	}
+	nodep->iterateChildren(*this);
+    }
+    virtual void visit(AstIfaceRefDType* nodep, AstNUser*) {
+	// May have changed cell names
+	// TypeTable is always after all modules, so names are stable
+	UINFO(8,"   IFACEREFDTYPE "<<nodep<<endl);
+	if (nodep->cellp()) nodep->cellName(nodep->cellp()->name());
+	UINFO(8,"       rename to "<<nodep<<endl);
+	nodep->iterateChildren(*this);
+    }
     //--------------------
     virtual void visit(AstNode* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
diff --git a/test_regress/t/t_interface_gen5.pl b/test_regress/t/t_interface_gen5.pl
new file mode 100755
index 000000000..1118f2e0e
--- /dev/null
+++ b/test_regress/t/t_interface_gen5.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v
new file mode 100644
index 000000000..0ef63226c
--- /dev/null
+++ b/test_regress/t/t_interface_gen5.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+
+// bug998
+
+interface intf
+  #(parameter PARAM = 0)
+   ();
+   logic val;
+endinterface
+
+module t1(intf mod_intf);
+   initial begin
+      $display("%d", mod_intf.val);
+   end
+endmodule
+
+module t();
+   generate
+      begin : TestIf
+         intf #(.PARAM(1)) my_intf;
+         t1 t (.mod_intf(my_intf));
+         initial begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   endgenerate
+endmodule