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Add error if always_comb has sensitivity list.

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This commit is contained in:
Wilson Snyder 2017-12-13 19:49:37 -05:00
parent 33eb0db6f8
commit 51787d68b9
4 changed files with 44 additions and 1 deletions
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2
Changes
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@ -13,6 +13,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Support string len() method. [Victor Besyakov]
**** Add error if always_comb has sensitivity list. [Arjen Roodselaar]
**** Fix modport outputs being treated as inputs, bug1246. [Jeff Bush]
**** Fix false ALWCOMBORDER on interface references, bug1247. [Josh Redford]

2
src/verilog.y
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@ -1719,8 +1719,8 @@ module_common_item<nodep>: // ==IEEE: module_common_item
// // Verilator only - event_control attached to always
| yALWAYS event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS, $2,$3); }
| yALWAYS_FF event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_FF, $2,$3); }
| yALWAYS_COMB event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_COMB, $2,$3); }
| yALWAYS_LATCH event_controlE stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_LATCH, $2,$3); }
| yALWAYS_COMB stmtBlock { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_COMB, NULL, $2); }
| loop_generate_construct { $$ = $1; }
| conditional_generate_construct { $$ = $1; }
| elaboration_system_task { $$ = $1; }

24
test_regress/t/t_lint_comb_bad.pl Executable file
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@ -0,0 +1,24 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
$Self->{vlt} or $Self->skip("Verilator only test");
compile (
verilator_flags2 => ["--lint-only"],
verilator_make_gcc => 0,
make_top_shell => 0,
make_main => 0,
fails => 1,
expect=>
q{%Error: t/t_lint_comb_bad.v:\d+: syntax error, unexpected '@'
.*},
);
ok(1);
1;

17
test_regress/t/t_lint_comb_bad.v Normal file
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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
always_comb @(*) begin
$stop;
end
endmodule