forked from github/verilator
Fix resolving inline nested interface names, bug1250.
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@ -19,6 +19,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix constant propagation across DPI imports of inout strings. [Victor Besyakov]
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**** Fix resolving inline nested interface names, bug1250. [Arjen Roodselaar]
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* Verilator 3.916 2017-11-25
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@ -35,6 +35,7 @@
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#include <unistd.h>
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#include <algorithm>
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#include <vector>
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#include VL_INCLUDE_UNORDERED_SET
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#include "V3Global.h"
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#include "V3Inline.h"
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@ -269,7 +270,7 @@ public:
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class InlineRelinkVisitor : public AstNVisitor {
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private:
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typedef std::set<string> RenamedInterfacesSet;
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typedef vl_unordered_set<string> RenamedInterfacesSet;
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// NODE STATE
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// Input:
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@ -412,9 +413,19 @@ private:
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string newname = m_cellp->name();
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if (nodep->inlinedDots() != "") { newname += "." + nodep->inlinedDots(); }
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nodep->inlinedDots(newname);
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if (m_renamedInterfaces.count(nodep->dotted())) {
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nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted());
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}
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for (string tryname = nodep->dotted(); 1;) {
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if (m_renamedInterfaces.count(tryname)) {
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nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted());
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break;
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}
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// If foo.bar, and foo is an interface, then need to search again for foo
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string::size_type pos = tryname.rfind(".");
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if (pos == string::npos || pos==0) {
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break;
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} else {
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tryname = tryname.substr(0, pos);
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}
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstNodeFTaskRef* nodep) {
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18
test_regress/t/t_interface_nest.pl
Executable file
18
test_regress/t/t_interface_nest.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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74
test_regress/t/t_interface_nest.v
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74
test_regress/t/t_interface_nest.v
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@ -0,0 +1,74 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by ____YOUR_NAME_HERE____.
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interface if1;
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integer var1;
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endinterface
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interface if2;
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if1 i1 ();
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integer var2;
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endinterface
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module mod1
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(
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input clk,
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input integer modnum, // Don't use parameter, want same module twice for better checking
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if2 foo
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);
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logic l1, l2;
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always_ff @(posedge clk) begin
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if (modnum==1) begin
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if (foo.i1.var1 != 1) $stop;
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if (foo.var2 != 2) $stop;
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end
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if (modnum==2) begin
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if (foo.i1.var1 != 1) $stop;
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if (foo.var2 != 2) $stop;
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end
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end
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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if2 i2a ();
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if2 i2b ();
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assign i2a.i1.var1 = 1;
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assign i2a.var2 = 2;
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assign i2b.i1.var1 = 3;
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assign i2b.var2 = 4;
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mod1 mod1a
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(
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.modnum (1),
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.clk (clk),
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.foo (i2a)
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);
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mod1 mod1b
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(
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.modnum (2),
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.clk (clk),
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.foo (i2a)
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);
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integer cyc = 0;
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always_ff @(posedge clk) begin
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cyc <= cyc+1;
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if (cyc==2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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21
test_regress/t/t_interface_nest_noinl.pl
Executable file
21
test_regress/t/t_interface_nest_noinl.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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top_filename("t/t_interface_nest.v");
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compile (
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v_flags2 => ["-Oi"],
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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