Fix resolving inline nested interface names, bug1250.

This commit is contained in:
Wilson Snyder 2017-12-13 19:42:49 -05:00
parent a0b2727c59
commit 33eb0db6f8
5 changed files with 130 additions and 4 deletions

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@ -19,6 +19,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix constant propagation across DPI imports of inout strings. [Victor Besyakov]
**** Fix resolving inline nested interface names, bug1250. [Arjen Roodselaar]
* Verilator 3.916 2017-11-25

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@ -35,6 +35,7 @@
#include <unistd.h>
#include <algorithm>
#include <vector>
#include VL_INCLUDE_UNORDERED_SET
#include "V3Global.h"
#include "V3Inline.h"
@ -269,7 +270,7 @@ public:
class InlineRelinkVisitor : public AstNVisitor {
private:
typedef std::set<string> RenamedInterfacesSet;
typedef vl_unordered_set<string> RenamedInterfacesSet;
// NODE STATE
// Input:
@ -412,9 +413,19 @@ private:
string newname = m_cellp->name();
if (nodep->inlinedDots() != "") { newname += "." + nodep->inlinedDots(); }
nodep->inlinedDots(newname);
if (m_renamedInterfaces.count(nodep->dotted())) {
nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted());
}
for (string tryname = nodep->dotted(); 1;) {
if (m_renamedInterfaces.count(tryname)) {
nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted());
break;
}
// If foo.bar, and foo is an interface, then need to search again for foo
string::size_type pos = tryname.rfind(".");
if (pos == string::npos || pos==0) {
break;
} else {
tryname = tryname.substr(0, pos);
}
}
nodep->iterateChildren(*this);
}
virtual void visit(AstNodeFTaskRef* nodep) {

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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

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@ -0,0 +1,74 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by ____YOUR_NAME_HERE____.
interface if1;
integer var1;
endinterface
interface if2;
if1 i1 ();
integer var2;
endinterface
module mod1
(
input clk,
input integer modnum, // Don't use parameter, want same module twice for better checking
if2 foo
);
logic l1, l2;
always_ff @(posedge clk) begin
if (modnum==1) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
if (modnum==2) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
end
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
if2 i2a ();
if2 i2b ();
assign i2a.i1.var1 = 1;
assign i2a.var2 = 2;
assign i2b.i1.var1 = 3;
assign i2b.var2 = 4;
mod1 mod1a
(
.modnum (1),
.clk (clk),
.foo (i2a)
);
mod1 mod1b
(
.modnum (2),
.clk (clk),
.foo (i2a)
);
integer cyc = 0;
always_ff @(posedge clk) begin
cyc <= cyc+1;
if (cyc==2) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
top_filename("t/t_interface_nest.v");
compile (
v_flags2 => ["-Oi"],
);
execute (
check_finished=>1,
);
ok(1);
1;